The Likely Delay of Intel's Core i5 Processor and Derivatives

Subject: Processors
Manufacturer: Intel

"I'll be gone til November..."

It has long been known that Intel will be releasing more mainstream versions of the Nehalem core, but these will be branded i5 and will utilize DMI for communications with the chipset instead of the server and workstation oriented QPI.  The other change will be cutting down the memory controller from a triple channel unit to a dual channel unit.  This allows a decent differentiation between the high end i7 and the i5.

The change from QPI to DMI is not a big one, in terms of overall performance, but it is a major change when you look at where the products will be offered.  As I mentioned before, QPI will only be offered in server and workstation products, where multiple sockets will be used.  This is the primary thrust of the technology, which is to enable efficient and high bandwidth connections between multiple processors in 2S and 4S systems.  DMI will provide enough aggregate bandwidth and low enough latency so as not to bottleneck the processor when it is communicating with the rest of the system.

DMI provides enough bandwidth for the majority of system needs outside of the graphics.  It will be curious to see how performance scales when motherboard manufacturers include another PEG slot hanging off of the chipset.

Going from triple channel to dual channel may or may not produce significant results, but it certainly doesn’t hurt to have gobs of available bandwidth.  From what we have seen so far with i7 testing and using only dual channels, the performance hit is not that significant.  The last major change is that the i5 will include 16 PCI-E lanes that can act as a 1 x 16 or a 2 x 8 controller.  So when everything comes out of the wash, the i5 should have a die size very comparable to the i7.

The problem that Intel is facing with the release of the i5 series of chips encompasses many issues.  The first, and foremost, is that the i5 may not give Intel all that great of an advantage in performance and power consumption as the current Core 2 series of chips.  The dual channel i5’s are likely to be faster overall per clock than the Core 2 series, but the differences look to be fairly minimal, depending on the application.  The single monolithic quad core takes up more overall die space than 2 x 45 nm Penryn based Core 2 parts.  We must also consider that there are still significant numbers of dual core products being sold, and a dual core Nehalem based product is not expected until early 2010. 

The other factor related to all of this is yields.  Intel (and all other manufactures) experiences an X amount of defects per cm square.  Getting out our trusty die calculator we can quickly assess how the economics of this situation unfold.  The Nehalem die that makes up the i7 is approximately 264 mm square, and from all indications it will be identical to what will be used in the i5, except of course with the third memory channel disabled as well as no QPI support.  On a 300 mm wafer, there can be approximately 221 gross die placed on the wafer.  This number in reality is less as there are dies that do not fully fit on the wafer, but without actually physically counting the amount of full dies on a wafer, we have to stick with the 221 number.  If we apply a defect density of .3 /cm squared and use the Murphy yield model, we have an overall yield of 47.9%.  That means there are a net total of 105 fully functional die without defect.

The new LGA-1156 socket does away with all QPI support and one memory channel.  Still, a goodly portion of those pins are for memory purposes... and integrated graphics support in the future.

Now we take a look at Penryn.  This part is 107 mm square.  So, when using the same wafer size, model, and defect rate, we see some dramatic differences.  First of all, there are approximately 585 gross die on the wafer (again, counting incomplete dies along the edge of the wafer), and with the same defect rate we see that yields have improved to 73.2%, giving a total of 428 net good die without defect.  These are of course the dual core chips, and it takes two of them to make a quad (higher math involved here).  Even if every good die was used in a quad product, we see that every Penryn wafer could theoretically product 214 quad core products.  This is still double the amount of what a Nehalem wafer can produce when dealing with similar defect densities.

These are very raw numbers, and they do not reflect procedures in place at Intel to recover defective dies.  Still, the numbers are striking, plus the Penryn products likely have even higher yields because they have been in production far longer than Nehalem.  Add to that the Penryn cores can be utilized in dual core SKUs as well as quad core, plus products addressing the mobile market.  Recently Intel just introduced the “S” series of quad cores which run at 65 watts TDP, so we can see that Intel has gotten production of Penryn down to a science.

We must also consider the chipset market.  In Q3 motherboard manufacturers ordered plenty of chipsets from Intel to support the Core 2 series of parts.  So when the economic downturn hit the industry, a lot of these manufacturers had large quantities of unused product sitting in their factories.  Demand fell precipitously and these manufacturers were stuck with a lot of inventory.  I believe that many of these manufacturers pressured Intel into not releasing their new i5, as they likely did not want to start trying to stock up on P55 based chipsets while previous gen P45, G45, and X38/X48 products languished in the parts bin.  The original plan was probably to start selling these P55 parts to motherboard manufacturers in late Q1 so they can build up an inventory of motherboards that can be offered for sale to consumers and OEMs by the end of Q2.  The G55 would have been offered shortly after that to fulfill the integrated demands of the i5 market.

While rather sparse looking, the integration of PCI-E onto the CPU does help to save a bit of space as compared to using a two chip motherboard setup.

With so many manufacturers still having plenty of inventory in hand, it would have been disastrous for Intel to try to push for a P55/i5 launch.  I would guess that many of the manufacturers would have refused to buy any kind of significant amount of chipsets from Intel to support the launch, and Intel would then be sitting on a lot of unsold i5 parts that simply have no place to run in.

While the chipset theory is a good one, I do believe that in the end Intel sees that when compared to Penryn, the Nehalem parts will not be nearly as successful as a midrange part from an economic standpoint.  It is better to keep Penryn chugging along, and at the end of 2009 introduce the first series of i5 parts at 45 nm, and quickly migrate to their 32 nm process to make the i5 much more successful and economically attractive.  The final portion to consider is that AMD is really only now competitive with their Shanghai core (which is also around 264 mm square) and it is primarily aimed at the Core 2 Quad products rather than the i7.  So, it makes much more business sense to keep Penryn going for Intel, as they really have nothing to lose with sticking it out.