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Intel Next Generation CPU Technology - Penryn and Nehalem

Subject: Processors
Manufacturer: Intel

Intel Details Penryn and Nehalem

UPDATE: If you are looking for a full in-depth look at the architecture and technology of the Intel Nehalem Core i7 processors, check out our most recent article on the subject!


Unlike all the previous years of Intel's very popular Intel Developer Forum, for 2007 the first and main IDF show will NOT be in San Francisco but will instead be in Beijing, China.  Apparently not many of the US media will be able to make the trip (making the decision to move it there somewhat in question) so in order to get the US media some sort of information on what will be discussed next month in Beijing, Intel had a brief one hour phone call today to highlight some future architectural changes.

Intel's Pat Gelsinger provides information on both Penryn, the 45nm update to the current Core 2 Duo line up due out this year, as well as Nehalem, 2008's next-generation architecture with tons of new features and possibilities.

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This slide highlights the goals for the Penryn family of updates to the Core micro architecture that we detailed just over a year ago.  Along with the move to the 45nm technology Intel wants to increase the performance per clock, or IPC, as well as the frequencies that the CPUs are able to run at within a similar power envelope. 

Back in January we first got information on the new High k + metal gate process technology that Intel was introducing into the 45nm production.

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This slide updates us on some more of the 45nm process technology information; most of the data was provided a couple of months ago as I mentioned above.  However, the ability to add 2x more transistors to a chip will maintaining a static die size and thermal envelope allow Intel to add features that can greatly increase overall performance.

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Here we see Intel's claims of both increased performance AND increased energy efficiency.  Also noted here is the inclusion of SSE4 into the instruction set on the Penryn family of processors as well as larger caches.  You can expect to see 8MB L2 caches become the standard on desktop models once Penryn is released, raising the transistor count to about 410 million for a dual core CPU and 820 million for a quad core.

It should also be no surprise that the "faster buses" that Intel mentions is the upcoming 1333 MHz FSB that has been talked about for some time.

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Pat was very pointed in discussion Penryn as NOT JUST A DIE SHRINK that there are quite a bit of architectural enhancements that will come with the new 45nm cores.  I already mentioned the larger cache sizes and SSE4 instruction set, but there are also changes to the execution pipeline that allow for increased speed in the Radix-16 divider (which affects square roots among many other things) as well as improved power down technology for energy efficiency. 

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This 45nm process technology will be making the rounds in all levels of Intel's product family from the server Xeon processors to the desktop Core 2 and even mobile CPUs. 

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For each processor family there will still be some optimized cores for each market's specific needs.  Mobile cores, for example, will have the most robust power down technology implemented in them and the enhanced dynamic acceleration technology for running only the number of cores necessary for the task at hand.  Desktop cores will be tweaked for higher clock speeds above 3.0 GHz while supplying up to 12MB of L2 cache and a relatively steady 95/130W TDP. 

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The Xeon family of server and workstation processors will have the much of the same optimizations as the desktop CPUs but will add support for 1600 MHz FSB (!!).

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