Review Index:

EVGA nForce 790i Ultra SLI Motherboard and Chipset Review

Author: Ryan Shrout
Subject: Motherboards
Manufacturer: eVGA

New Chipset Technologies

Even though the technology is not knew the couple of interesting features were added to the nForce 790i Ultra SLI chipset to improve multi GPU performance with NVIDIA graphics cards.  Both of these features were originally implemented on the nForce 200 bridge chip on the nForce 780i motherboards.

These improved CPU and GPU communication protocols help make SLI latency lower than it would be on other chipsets.  The PCIe controller inside the nForce 790i north bridge has an ability to forward messages from one GPU to any other GPU without the need for the primary processor to be involved.  The technology is called posted-write shortcut, or PWShort.

The second technology is very similar in that it takes a single command from the primary processor and distributed to all of the NVIDIA GPU use attached to the north bridge.  This command can also be in the form of data such as geometry, textures or other rendering data from the CPU.  Both of these technologies are an attempt to lower in the congestion or latency required for chips to communicate across the front side bus.

Another interesting feature on this chipset is the ability to support DDR3 memory at speeds up to 2000 MHz.  This is obviously an overclocked setting but as long as you have memory modules capable of running at the speeds the process is pretty easy to setup.

The new memory controller integrated on the nForce 790i Ultra SLI chipset was specifically designed for this feature and allows you to run these speeds at relatively low voltages.  Because Intel's processors still used in external memory controller, at least for the time being, NVIDIA had to build one on its own.  While they did have success with their DDR and the DDR2 controllers it took quite a while for a DDR3 controller to come out of the company.  They have improved on the data fetching algorithms and arbitration algorithms on the memory controller and have implemented a dynamic, deterministic algorithm that will supposedly lower latency across the platform.  Of course the only real way to test this is in benchmarks so we'll be doing this soon.

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