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ARM Introduces DynamIQ Technology

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Subject: General Tech
Manufacturer: ARM

New "Fabric" for ARM

It is not much of a stretch to say that ARM has had a pretty impressive run for the past 10 years since we started paying attention to the company from a consumer point of view.  It took 22 years for ARM to power 50 billion chips that had been shipped.  It took another 4 years to hit the next 50 billion.  Now ARM expects to ship around 100 billion chips in the next four years.
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Last year we saw the introduction of multiple technologies from ARM in the shape of the latest Cortex-A CPUs and a new generation of Mali GPUs.  ARM has been near the forefront of applying their designs to the latest, cutting edge process technologies offered by Samsung and TSMC.  This change of pace has been refreshing considering that a few years ago they would announce a new architecture and expect to see it in new phones and devices about 3 years from that point.  Intel attempted a concerted push into mobile and ARM responded by tightening up their portfolio and aggressively pushing release dates.
 
This year appears no different for ARM as we expect new technologies to be announced again later this year that will update their offerings as well as process technology partnerships with the major pure-play foundries.  The first glimpse of what we can expect is ARM's announcement today of their DynamIQ technology.
 
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DynamIQ can be viewed as a portfolio of technologies that will power the next generation of ARM CPUs, GPUs, and potentially accelerators.  This encompasses power delivery, power control, connectivity, and topologies.
 
 
The most visible aspect of this technology is the new single cluster design.  Previous clusters in big.LITTLE implementations were a bit more static in what they could achieve.  Certain numbers of CPUs had to be present, power delivery was not granular, and most power savings were due to turning off CPU cores.  ARM has changed this with DynamIQ.  It now allows up to eight CPU cores of different capabilities.  It also allows a great amount of flexibility in what cores it uses in any type of numbers that a partner decides they need.  If a partner determines that their usage case requires 1 big core, 3 small cores, and a dedicated media accelerator then it has the ability to design such a SoC without limitations.
 
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Power is one of the primary driving factors of mobile performance and ARM is addressing this straight one.  Previous clusters could not dynamically change power per CPU, except of course if they were asleep.  Now there is individual control of each CPU in the cluster so it can have unique clock and power characteristics.
 
ARM is allowing the use of specialized accelerators provided by 3rd party designers that can be integrated into DynamIQ designs.  Previously this was not possible with ARM designs and it took guys like Qualcomm with an ISA license to develop their own specialized units.  ARM is opening up DynamIQ so partners can develop their own accelerators and attach it to the shared bus without any legal or license rammifications.
 
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There are some caveats for implementing this technology.  Previous Cortex cores will not be able to work in DynamIQ.  This technology is fundamentally different from previous implementations and requires a low level rework on the cores and their caches.  So this means that we will see new cores being introduced this year that will fit on the DynamIQ platform.  These new cores will be backwards compatible with previous ARM cores, but previous ARM cores will not be able to be integrated into DynamIQ.  The ISA will be updated to ARMv8.2, but it is still AMBA compliant.
 
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Memory speeds and power consumption will also be addressed in this release.  ARM promises greater performance from memory as well as core to core communications.  This also includes good memory performance to third party accelerators that attach to DynamIQ.  ARM is not looking to kneecap their partners with limitations on core complexes and external accelerators.  This will make the platform more desirable to those wishing to address growing markets such as self-driving autos, deep learning, and AI applications.
 
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ARM continues to be the primary player in the mobile market and they work closely with their partners throughout the world to improve power consumption, performance, and flexibility.  DynamIQ is the first big shot of the year from ARM, but looking at what they have discussed here we can expect many more announcements to come.

March 21, 2017 | 01:58 AM - Posted by BlackDove (not verified)

Was a pretty smart idea for the Japanese to buy them. First real useful exascale computer will be Fujitsu ARM v8 CPU based.

March 21, 2017 | 09:54 AM - Posted by Anonymous (not verified)

ARM holdings is owned by SoftBank and other international investors now, and not only just SoftBank. SoftBank appears to be moving more away from the telecommunications/phone carrier/technology market towards the investment/capital markets!

March 21, 2017 | 12:19 PM - Posted by Jeremy Hellstrom

Yup, they are indeed. https://www.pcper.com/news/General-Tech/SoftBank-Plans-Sell-25-ARM-Holdi...

March 21, 2017 | 09:07 AM - Posted by willmore

So, if each core can have its own core voltage, where is that regulation going to happen? Are we expecting that PMU (Power Management Units) chips for ARM are going to go from 1 CPU_VCC to 8?

Or are they doing like Intel did with mobile Haswell and moving the regulation for the cores on die?

This is a very non-trivial question and this kind of integration has been poorly standardized in the ARM ecosystem and could really use some leadership. There is a lot of power efficiency to be had here if it's done right.

March 21, 2017 | 12:18 PM - Posted by Josh Walrath

They did not go into that level of detail, but one would expect a lot more being done closer to the cores to enable this functionality.  You are right, a lot of net improvements could be had with a proper implementation.

March 22, 2017 | 06:41 PM - Posted by willmore

Thank you, sir!

March 21, 2017 | 09:48 AM - Posted by Anonymous (not verified)

So this is a data and control fabric and ARM Holdings' customers will be using this on die and off?

Arm Holdings(SoftBank) needs to start to maybe develop a wider order superscalar reference design for maybe some server customers to try out. And there is always the question of if Jim Keller's/Team's other CPU K12 project will make it to market, I'd love to see maybe a K12 custom very wide order superscalar AMD design for the server room with maybe 64 or more K12 custom ARM cores running those new ARM ISA SVE(Scalable Vector Instructions) and SVE is scalable from 128-bits to 2048-bits in 128-bit increments! Maybe with a beefed up Infinity Fabric for some number crunching workloads.

If IBM can make some very very wide order superscalar RISC ISA based power8/powe9 designs then ARM Holdings, or AMD and others should be able to do the same for any ARMv8 RISC ISA designs. There has been a lot of ARM in the server room related announcements lately from many of the ARM Holdings ARMv8A ISA licensees that build their own custom micro-architectures that run the ARMv8A or newer ISA.

March 21, 2017 | 12:17 PM - Posted by Josh Walrath

This isn't Infinity Fabric afaik.  ARM usually doesn't license a tech from a firm to only then relicense it out to partners.

It will definitely be on-die, but unknown if functionality exists off die (connecting two dies).

March 21, 2017 | 02:07 PM - Posted by Anonymous (not verified)

Yes but K12 is AMD's custom ARMv8A ISA runnng micro-arch so I'd expect that K12 would use AMD's Infinity Fabric rather than any other IP.

Also I'm seeing some posts/rumors that are maybe indicating that AMD's K12 will be an even wider order superscalar design than Zen. So it will be interesting to see just how much execution width AMD's K12 cores will offer for any AMD server SKUs that use the K12 cores/micro-arch. It takes a lot less die space to implement a RISC ISA design like the ARMv8A ISA designs. And look at the Power8 RISC ISA besed design with its 8 wide instruction decoders feeding into 16 execution units/pipelines per power8 core with each power8 core supporting SMT8/8 processor threads per core.

So maybe ARM's DynamIQ is similar to AMD's Infinity Fabric in its reach, so for any of ARM Holdings regular licensees they can license ARM Holding's DynamIQ IP instead of having to create their own from scratch.

For ARM Holdings' other regular licensees(The ones that mostly used ARM Holdings' off the shelf reference design cores) this DynamIQ will be licensed and used for all sorts of uses phone to server for those licensees without the in-house chip design means to create the IP on their own.

AMD, Apple/Nvidia/some others are ARM Holdings TOP Tier architectural licensees. So they just license the ARMv8A/ISA and roll their own custom designs. Apple's A series cores including the A7/later designs are twice as wide order superscalar designs than any of ARM Holdings refrence design cores, and maybe AMD's K12 will be even wider than that. Nvidia's Denver/Denver1 cores are a little bit beefer than even Apple'a A serise designs but to this date I do not think there is any custom ARM core on the market yet that supports SMT! AMD's K12, other companies, custom ARMv8A ISA running designs may change that for SMT in the future.

March 27, 2017 | 04:28 AM - Posted by Mobile_Dom

so, in theory, companies could make an SOC with 2 future A73s, 2 Future A35s, and a future Cortex M7 for super low power screen off stuff?

ARM has made some very interesting strides here.

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