Review Index:

How 3D XPoint Phase-Change Memory Works

Introduction, How PCM Works, Reading, Writing, and Tweaks

I’ve seen a bit of flawed logic floating around related to discussions about 3D XPoint technology. Some are directly comparing the cost per die to NAND flash (you can’t - 3D XPoint likely has fewer fab steps than NAND - especially when compared with 3D NAND). Others are repeating a bunch of terminology and element names without taking the time to actually explain how it works, and far too many folks out there can't even pronounce it correctly (it's spoken 'cross-point'). My plan is to address as much of the confusion as I can with this article, and I hope you walk away understanding how XPoint and its underlying technologies (most likely) work. While we do not have absolute confirmation of the precise material compositions, there is a significant amount of evidence pointing to one particular set of technologies. With Optane Memory now out in the wild and purchasable by folks wielding electron microscopes and mass spectrometers, I have seen enough additional information come across to assume XPoint is, in fact, PCM based.

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XPoint memory. Note the shape of the cell/selector structure. This will be significant later.

While we were initially told at the XPoint announcement event Q&A that the technology was not phase change based, there is overwhelming evidence to the contrary, and it is likely that Intel did not want to let the cat out of the bag too early. The funny thing about that is that both Intel and Micron were briefing on PCM-based memory developments five years earlier, and nearly everything about those briefings lines up perfectly with what appears to have ended up in the XPoint that we have today.

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Some die-level performance characteristics of various memory types. source

The above figures were sourced from a 2011 paper and may be a bit dated, but they do a good job putting some actual numbers with the die-level performance of the various solid state memory technologies. We can also see where the ~1000x speed and ~1000x endurance comparisons with XPoint to NAND Flash came from. Now, of course, those performance characteristics do not directly translate to the performance of a complete SSD package containing those dies. Controller overhead and management must take their respective cuts, as is shown with the performance of the first generation XPoint SSD we saw come out of Intel:

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The ‘bridging the gap’ Latency Percentile graph from our Intel SSD DC P4800X review.
(The P4800X comes in at 10us above).

There have been a few very vocal folks out there chanting 'not good enough', without the basic understanding that the first publicly available iteration of a new technology never represents its ultimate performance capabilities. It took NAND flash decades to make it into usable SSDs, and another decade before climbing to the performance levels we enjoy today. Time will tell if this holds true for XPoint, but given Micron's demos and our own observed performance of Intel's P4800X and Optane Memory SSDs, I'd argue that it is most certainly off to a good start!

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A 3D XPoint die, submitted for your viewing pleasure (click for larger version).

You want to know how this stuff works, right? Read on to find out!

How PCM Works

To understand how XPoint reads and writes bits, let’s start with how phase change materials work, and to do that we need to know what makes a material PCM capable in the first place:

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Periodic Table. Metalloids in yellow. Chalcogens blue boxed. source

Phase change materials are generally alloys of metalloids. Metalloids are elements that share properties with metals and non-metals. They act as insulators at room temperature and as conductors when heated (or when doped). Alloys of varying mixtures of the semimetals have been experimented with for decades. Boron is mainly used for doping, and Polonium is unstable and radioactive, so we won’t be seeing much of that one :). Silicon is great for standard transistors and other semiconductors, but less than optimal as a phase change material. That leaves Germanium (Ge), Arsenic (As), Antimony (Sb), and Tellurium (Te). Alloying these together results in a chalcogenide (kal-kuh-juh-nahyd), which in the context of this article is a compound containing a Tellurium anion (Te is the only stable metalloid belonging to the chalcogen group of the periodic table). Once mixed in the proper proportions, these materials offer some rather unique properties:

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Specifically, metalloid alloys have multiple stable states that each come with their own distinct resistance characteristics. These can be manipulated by heating and cooling the material in various ways. The amorphous state resembles a glass, while the crystalline state more closely resembles a metal.

Reading and Writing Phase Change Memory

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Attributes of PCM materials. Sources: 1,2

Ok, let's explain what is going on here. Voltage is applied across a section of chalcogenide material. If the material is in an amorphous (mixed) state, it does not begin to conduct until the threshold voltage (Vth) is exceeded. Once conducting, as voltage increases further, so does the current. Since the material is now acting resistive, it dissipates heat and therefore increases in temperature. If held at the ‘set’ (1) voltage, the material reaches ~350C, which is not hot enough to become molten, but *is* warm enough for its molecules to realign into a crystalline structure if the temperature is maintained for ~100 nanoseconds. Once formed, the crystalline structure behaves like a resistor and remains even after the voltage is removed and the material cools. Once in the set state, applying 0.5V would result in ~0.5mA (using the above example). The voltage no longer needs to meet a threshold in order for the material to conduct, and its response follows the plot line marked ‘crystalline’.

To reset the cell, we apply a much higher voltage, pushing currents and temperatures high enough (~600C) to heat the material to a molten state. This melts down the crystalline structure. The voltage is then removed and the material rapidly cools, passing through the crystallization temperature region too quickly to form any crystal structure, ‘freezing’ it in the amorphous state. It is now ‘reset’ (0), and applying that same 0.5V will result in near zero current. I should point out that we don’t need nearly that high of a voltage to perform a read, as even 0.1V would produce a readable difference in current between the two states used in our example.

An interesting thing to note about the above is that there is no ‘erase’ required before programming a cell as is the case with NAND flash. With PCM cells, we can perform a set or reset operation by simply applying the associated voltage/time profile without regard for the previously set state. Unlike NAND which must be written in pages (KB) and erased in even larger blocks (MB), PCM data can be overwritten ‘in-place’, and single bit overwrites are possible without disturbing adjacent cells.

Tweaking the Formula

Intel and Micron would have you believe that the stuff that makes up XPoint is an ancient Chinese secret. Well, it’s not. The common phase change alloy is a 2:2:5 stoichiometric ratio of Germanium, Antimony, and Tellurium. Ge2Sb2Te5, dubbed ‘GST’ for short. As is with most alloys, there are many slight variations possible to the recipe, and that is where the manufacturer-specific secrets come into play. That said, we do have some clues as to what might have been tweaked from a 2010 Micron presentation:

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Those developing PCM technology will naturally finely tune the mixture to try and improve performance. Above we see an excerpt from a Micron brief showing how slightly increasing the concentration of Antimony (Sb) helped reduce the reset resistance (reducing the voltage needed), as well as reducing the time needed for a set operation. There are also external factors related to cell selection that might require tweaking the ratios further, which we will touch on shortly.

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You might think phase change alloys are so exotic that you have never seen or held them, but you are likely wrong. Rewritable optical discs (CD-RW/DVD-RW) are extremely close cousins to the materials found in XPoint. Optical discs used Silver and Indium in place of the Germanium found in GST, which naturally changed the properties of the alloy. ‘Blank’ media was crystalline, and pits were written by heating spots by pulsing the write laser. The spots then quickly cooled without a chance to recrystallize, forming darker areas that could later be read as differences in reflectivity. Discs were erased by applying a lower power laser which started the recrystallization process (these alloys could continue crystalizing after the laser passed the area). Other metalloid alloy variants were used in various optical media technologies, aiming to improve the number of erase cycles and other performance characteristics. DVD-RAM actually used GST compounds but relied on its changing optical properties as opposed to electrical conductivity.

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June 2, 2017 | 12:32 PM - Posted by Dvon of Edzore

Allyn-- Thank you for a great article. Nice to see Stanford Ovshinsky get more vindication. I recall an early magazine article that pretty much treated him and Ovonics as a curiosity of no practical use. Amazing how much of the 21st century has this self-taught inventor's fingerprints on it.

June 3, 2017 | 01:56 PM - Posted by Allyn Malventano

Yeah, I read a lot about him while researching this piece. Interesting guy / family.

June 2, 2017 | 12:55 PM - Posted by MRFS

Ditto that: I'm filing a Provisional Patent Application
for a proprietary device that will clone Allyn many times
over, with royalties to his estate and/or favorite charity.

Throw in a generous life insurance policy too!

p.s. We LUV you, Allyn!


June 2, 2017 | 05:28 PM - Posted by MRFS

> A 3D XPoint die, submitted for your viewing pleasure

we suspect this is an aerial photo
of a corn field in Nebraska,
w/ a few Photoshopped red streaks
added for effects.

June 3, 2017 | 01:03 PM - Posted by Allyn Malventano

Fun fact: photo was taken from 1 meter away, with horrible lighting.

June 3, 2017 | 01:30 AM - Posted by Lucidor

If Intel didn't want it spoken 'XPoint', they shouldn't have written it that way.

June 3, 2017 | 01:56 PM - Posted by Xebec

Very interesting Allyn - thank you..

The "gets smaller, becomes more reliable" is quite the interesting attribute, and I liked the comparison to DVDRAM/RW.

One side note - your ' ~ infinite ' stat for DRAM endurance had me look up DRAM endurance. Micron says the standard accepted endurance for DRAM is ">1E15 cycles". pg 9:

I'm not sure how to convert this to a power of 10 though :(. It will be interesting to see how Optane approaches DRAM reliability over time.

June 4, 2017 | 01:06 AM - Posted by Allyn Malventano

That's a high enough endurance that you might start to consider it effectively infinite :)


Also, note that briefing states >1E15, meaning a *minimum*, likely based on failure rates in general as opposed to the number of times you can rewrite a specific bit.

June 3, 2017 | 03:57 PM - Posted by MRFS

1E15 = 1.0 x 10^15

e.g. 1E2 = 1.0 x 10^2 = 100
("2" after "E" is the number of zeroes)


1E15 = 1,000,000,000,000,000 = one quadrillion

Any word about the 2.5" U.2 Optane?

p.s. I personally feel that non-volatile DRAM
is easily one of THE most significant developments
currently underway in the field of computer R&D.
(Just my own bias, OK?)

June 3, 2017 | 09:58 PM - Posted by Xebec

Thanks re: 1Ex = 1.0 x 10^X

June 3, 2017 | 08:39 PM - Posted by virtualvoid

Fantastic article, thanks!

June 5, 2017 | 10:43 PM - Posted by Uniblaab2

Yeah. I agree, great article. It also shows that some inventions are just re-configuring things that are already known - using them in new ways. I bet that since pcm now have a foot in the memory door, that it wont be long when someone figures out ways to use them in other ways. Now that the ovonic switch is a mass production reality, how long before its used as a true brickable chip. If you enter the wrong password wrong 10 times, a voltage is sent to all of the switches and resets everything to null. No erase cycle needed, just one ovonic shot of current across all nodes.
Phase change uefi/bios. One chip that has two different ovonic switches. The first would allow a part of the memory to be used as flash memory. The second would allow a sectioned off section of the same memory to be used as a type of firmware.

PCM on silicone. The increased speed of transistors, with the only slightly lesser speed of reprogrammable memory.

Suppose the chemistry could be precisely controlled so it would be understood at what voltage a switch would open. An overvoltage would/could divert excess voltage away from sensitive circuitry. A nanometer sized resettable fuse! Also a current interrupter and posibly a voltage divider with sub microvoltage divisions. I dont know where they would be used but make it and they will come.

June 9, 2017 | 02:34 PM - Posted by TylerDong

I am glad that I have the opportunity to read this article, I have published the article in their own community website, the address link to , I hope everyone interested in the SSD can join together to learn.

October 4, 2017 | 01:28 PM - Posted by Jeremy Hellstrom

Not cool to copy and paste Al's entire review to your site.  We will be in touch.

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