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How 3D XPoint Phase-Change Memory Works

Selectors, Scaleability, and Conclusion

Selectors

Ok, so now that we have a viable phase change memory material, we need to pack it together as tightly as possible. The standard method of addressing types of memory are with bit and word lines (aka columns and rows). Generally speaking, the control circuitry selects a given section of memory by enabling its associated bit and word lines, and the data is retrieved by measuring and translating some parameter (voltage or current) into a usable output. With NAND flash memory, each cell is actually part of a transistor circuit, and the current charge of the cell controls the conductivity of its associated transistor - but only when that transistor has been energized by the control circuitry.

When switching to a memory technology that acts purely resistive, we’d like to just slap it all together in the highest density possible. That is an option, and it’s called ‘crossbar’, which is what is used for XPoint (you’ve likely seen the popular crosshatch design in their press photos by now), but there is a significant problem with this particular setup:

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source

That problem is with parallel resistance. Creating a current path through a single cell by energizing its associated word and bit lines not only applies a voltage to the desired cell, it also creates parallel paths through the adjacent junctions. The parallel paths are generally a higher resistance as the ‘sneak’ currents must pass through multiple cells in series to create each possible parallel path, but there are *many* of those parallel circuits - enough to alter the measured output, rendering the memory unreadable.

What we need to fix this is called a selector, which will enable only the circuit path we desire. This is typically a transistor, diode, or any other switching method that will prevent (or minimize the impact of) the parallel paths around the cell we want to access.

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Possible selector types for use with phase change memory. Note the rightmost entry under ‘cell size’. That’s a good (6-year old) hint!

Unfortunately, most of the methods involving transistors negate the density gains seen from the compact crossbar layout. Recall that we are after densities *higher* than flash memory, so even a single transistor per cell is unacceptable here. Diodes are smaller and can be used, and there has been a lot of research into that avenue, but it remains an overly complex solution. There is a simple method which avoids transistors and diodes entirely, and even shares the same materials used to store the bits in the first place - so long as we can get the material chemistry just right. It is possible to have a circuit element that reduces its resistance only with sufficient voltage applied, meaning only the selected cell will see current flow, with negligible current flowing through the parallel paths.

If this sounds like the phase change memory itself, you’d be right, but it needs to be a slightly different alloy to function as a reliable switch. Specifically, we want the selector to have a consistent behavior each time it is enabled. We don’t want it to ever stick in the ohmic ‘set’ state. This is accomplished by doping the material with additional elements (e.g. Arsenic) that prevent crystallization, so we are left with a material that only conducts once a sufficient voltage threshold is exceeded.

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An Ovonic Threshold Switch (OTS). Each time the voltage is completely removed and the material cools, it returns to its amorphic state, never crystalizing and therefore not behaving as a ‘memory’ but as a switch.

This is called an Ovonic Threshold Switch (OTS). If we place an OTS in series with each PCM cell in the crossbar layout, we can only access the PCM cell once we have applied enough voltage to cause the OTS to conduct. Since the parallel paths consist of multiple OTS/PCM pairs connected in series, only the OTS of the selected cell sees enough voltage to turn on. The OTS’s in the parallel paths all remain in the off state and do not conduct, enabling successful reading of the selected cell with minimal parallel circuit interference. Those familiar with NAND flash might be aware of a phenomenon called read disturb, where a read operation can slightly change the stored electrical charge of adjacent cells. Since the read operation for PCM falls well below the crystallization temperature of the cell being read, nearby cells will be even colder and see negligible sneak currents, meaning no chance for disturbing any of the cell states while reading - not even that of the cell being read.

Everything we discussed earlier about setting or resetting the GST material still applies for programming a cell with an OTS selector, but the voltage profile and materials used within the OTS+GST pair must be adjusted slightly to ensure the switch remains ‘on’ while the GST is held at its lower crystallization temperature for long enough to program a set state.

Scalability

Shrinking:

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We’re all used to die shrinks leading to lower endurance and other scaling problems for NAND flash memory, but the case is actually the opposite for PCM devices. Since the GST material is resistive and has mass that must be heated while also being thermally insulated from its surroundings, the smaller the better! As a matter of fact, one of the main things holding PCM technology back all of these years was that the required program currents were too high to be practical in a high-density device. Smaller cells translate to lower resistances across smaller areas, meaning less power needed to heat the smaller space, and therefore lower voltages and currents are needed to program a given cell. There is technically room to shrink further, but the materials science is extremely complex to even get perfectly segmented GST layers on a standard silicon wafer in the first place, so let’s be happy Intel and Micron have succeeded with a 20nm pitch for now.

Stacking:

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According to TechInsights, XPoint uses a 20nm node for the word and bit lines, with a cell size of 0.00176 um2. The thin line across the above image is two layers of stacked PCM cells.

XPoint is currently only using two layers, and those layers are extremely thin compared to the control circuitry, which sits beneath the XPoint array. This leaves plenty of room to scale additional layers, and therefore additional capacity. There are of course limits to this stacking, as they introduce additional parallel paths that could allow sneak currents to interfere with the selected cell. OTS selectors help as we described earlier, but their 'off' resistance is not infinite, meaning we can not scale significantly without supporting improvements elsewhere.

Before we move on, a quick note that the TechInsights source above states that PCM is used in XPoint, and they should know considering they are one of the groups slicing up and analyzing it.

MLC (including TLC, QLC):

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Examples of multiple bits per (PCM) cell from Macronix (2007), Numonyx (2008), and IBM (2011)

While we have only seen one bit per cell (SLC) in today’s XPoint, the possibility of multiple bits per cell does exist. That may be complicated by Intel/Micron’s choice to use an OTS selector, but it should still be a possibility once the XPoint implementation has sufficiently matured.

Conclusion

Ok, so we’ve covered how to program PCM cells, how to pack them together as tightly as possible, and which selector type makes that possible. It looks like we’ve figured out what makes XPoint memory tick, but there are a few more proof points to bring up:

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The above image is sourced from, as stated in the graphic, a 2009 joint Intel-Numonyx presentation. For those unaware, Micron acquired Numonyx in 2010, and at that time, Intel and Micron were very heavily ramping up their joint memory technology efforts. It stands to reason that once Intel and Micron figured out that XPoint was a feasible product that could net them a significant technological advantage, that it was time to stop presenting it as a ‘possible future memory’ and instead quietly focus on making it mass producible.

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We did see one last presentation at the 2011 Flash Memory Summit before Micron went completely silent. Above we can see that Micron had reached the state where there was a significant statistical distinction between the set and reset states of a 2Mbit block of XPoint, and that its endurance had reliably reached the 1 million cycle range.

…so, as it turns out, the super-secret technology used in XPoint memory has been right in front of us for nearly a decade! Sure, there may be some slight developmental differences in the years since Micron and Numonyx were actively presenting on their technology, but it is unlikely that the core of the tech was radically changed since those briefings. Circling back to why Intel was so adamant about XPoint not being phase change based, our best guess is that it was just them overzealously protecting their IP from competitors combined with some exceedingly critical semantics that would have you believe a zebra is not a horse. As far as things look now, if it looks like a duck and quacks like a duck, it's probably PCM after all!

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June 2, 2017 | 12:32 PM - Posted by Dvon of Edzore

Allyn-- Thank you for a great article. Nice to see Stanford Ovshinsky get more vindication. I recall an early magazine article that pretty much treated him and Ovonics as a curiosity of no practical use. Amazing how much of the 21st century has this self-taught inventor's fingerprints on it.

June 3, 2017 | 01:56 PM - Posted by Allyn Malventano

Yeah, I read a lot about him while researching this piece. Interesting guy / family.

June 2, 2017 | 12:55 PM - Posted by MRFS

Ditto that: I'm filing a Provisional Patent Application
for a proprietary device that will clone Allyn many times
over, with royalties to his estate and/or favorite charity.

Throw in a generous life insurance policy too!

p.s. We LUV you, Allyn!

:)

June 2, 2017 | 05:28 PM - Posted by MRFS

> A 3D XPoint die, submitted for your viewing pleasure

FAKE NEWS ALERT:
we suspect this is an aerial photo
of a corn field in Nebraska,
w/ a few Photoshopped red streaks
added for effects.

June 3, 2017 | 01:03 PM - Posted by Allyn Malventano

Fun fact: photo was taken from 1 meter away, with horrible lighting.

June 3, 2017 | 01:30 AM - Posted by Lucidor

If Intel didn't want it spoken 'XPoint', they shouldn't have written it that way.

June 3, 2017 | 01:56 PM - Posted by Xebec

Very interesting Allyn - thank you..

The "gets smaller, becomes more reliable" is quite the interesting attribute, and I liked the comparison to DVDRAM/RW.

One side note - your ' ~ infinite ' stat for DRAM endurance had me look up DRAM endurance. Micron says the standard accepted endurance for DRAM is ">1E15 cycles". pg 9:
https://www.flashmemorysummit.com/English/Collaterals/Proceedings/2010/2...

I'm not sure how to convert this to a power of 10 though :(. It will be interesting to see how Optane approaches DRAM reliability over time.

June 4, 2017 | 01:06 AM - Posted by Allyn Malventano

That's a high enough endurance that you might start to consider it effectively infinite :)

 

Also, note that briefing states >1E15, meaning a *minimum*, likely based on failure rates in general as opposed to the number of times you can rewrite a specific bit.

June 3, 2017 | 03:57 PM - Posted by MRFS

1E15 = 1.0 x 10^15

e.g. 1E2 = 1.0 x 10^2 = 100
("2" after "E" is the number of zeroes)

Thus,

1E15 = 1,000,000,000,000,000 = one quadrillion

Any word about the 2.5" U.2 Optane?

p.s. I personally feel that non-volatile DRAM
is easily one of THE most significant developments
currently underway in the field of computer R&D.
(Just my own bias, OK?)

June 3, 2017 | 09:58 PM - Posted by Xebec

Thanks re: 1Ex = 1.0 x 10^X

June 3, 2017 | 08:39 PM - Posted by virtualvoid

Fantastic article, thanks!

June 5, 2017 | 10:43 PM - Posted by Uniblaab2

Yeah. I agree, great article. It also shows that some inventions are just re-configuring things that are already known - using them in new ways. I bet that since pcm now have a foot in the memory door, that it wont be long when someone figures out ways to use them in other ways. Now that the ovonic switch is a mass production reality, how long before its used as a true brickable chip. If you enter the wrong password wrong 10 times, a voltage is sent to all of the switches and resets everything to null. No erase cycle needed, just one ovonic shot of current across all nodes.
Phase change uefi/bios. One chip that has two different ovonic switches. The first would allow a part of the memory to be used as flash memory. The second would allow a sectioned off section of the same memory to be used as a type of firmware.

PCM on silicone. The increased speed of transistors, with the only slightly lesser speed of reprogrammable memory.

Suppose the chemistry could be precisely controlled so it would be understood at what voltage a switch would open. An overvoltage would/could divert excess voltage away from sensitive circuitry. A nanometer sized resettable fuse! Also a current interrupter and posibly a voltage divider with sub microvoltage divisions. I dont know where they would be used but make it and they will come.

June 9, 2017 | 02:34 PM - Posted by TylerDong

I am glad that I have the opportunity to read this article, I have published the article in their own community website, the address link to http://www.pkssd.com/bbs/portal.php?mod=view&aid=68 , I hope everyone interested in the SSD can join together to learn.

October 4, 2017 | 01:28 PM - Posted by Jeremy Hellstrom

Not cool to copy and paste Al's entire review to your site.  We will be in touch.

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