Toshiba and Western Digital announce QLC and 96-Layer BiCS Flash

Subject: Storage | June 28, 2017 - 09:49 PM |
Tagged: wdc, WD, toshiba, QLC, nand, BiCS, 96-layer, 3d

A couple of announcements out of Toshiba and Western Digital today. First up is Toshiba announcing QLC (4 bit per cell) flash on their existing BiCS 3 (64-layer) technology. QLC may not be the best for endurance as the voltage tolerances become extremely tight with 16 individual voltage states per cell, but Toshiba has been working on this tech for a while now.

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In the above slide from the Toshiba keynote at last year's Flash Memory Summit, we see the use case here is for 'archival grade flash', which would still offer fast reads but is not meant to be written as frequently as MLC or TLC flash. Employing QLC in Toshiba's current BiCS 3 (64-layer) flash would enable 1.5TB of storage in a 16-die stack (within one flash memory chip package).

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Next up is BiCS 4, which was announced by Western Digital. We knew BiCS 4 was coming but did not know how many layers it would be. We now know that figure, and it is 96. The initial offerings will be the common 256Gbit (32GB) capacity per die, but stacking 96 cells high means the die will come in considerably smaller, meaning more per wafer, ultimately translating to lower cost per GB in your next SSD.

While these announcements are welcome, their timing and coordinated launch from both companies seems odd. Perhaps it has something to do with this?


June 29, 2017 | 10:32 AM - Posted by Clmentoz (not verified)

What the Hex! The memory controller on any quad level cell NAND is sure to be very busy performing error correction on any stale data. So I hope that they are adding a little more processing power to the controller on any SKUs with QLC NAND. Can the QLC NAND be gracefully degraded to TLC or MLC, at the cost of some capacity, as the NAND ages.

Looking at that 15nm process node tells me that there are less atoms for longer term state retention unless the 3D NAND is fatter in the Z dimension than the X and Y to allow for more atoms and better long term state retention.

June 29, 2017 | 12:51 PM - Posted by Lord Binky (not verified)

That makes it interesting to see what will happen when it's eventually read/write treated. Maybe the have a material trick out something up their sleeve so it clears out the inevitable charge build up. Possible they're just going to just apply the lessons learned on the production scale and apply it to the memristor tech as the next step driving upgrades from those who aren't satisfied with the long term performance. Makes for a great position for sales, you get a taste of the performance then a new technology fixes everyone's major issues comes along soon after.

June 29, 2017 | 02:56 PM - Posted by Clmentoz (not verified)

As long as there are enough atoms in the cell to hold the state for a long period of time by making the Z axis thicker relative to the X and Y with the newer 3D stacking/deposition technology then at 15nm things can be made to perform like a larger planier node. Because even TLC has its issues at below 40nm cell size, and goin QLC is only going to make cell state matters worse. That BiCS 3 proceess needs to be looked at more in depth and that ReRam IP appears be some form of bulk materal storage similar to XPoint.

With Micron willing to license its QuantX/XPoint IP to other Memory/SSD makers, maybe Samsung/Others will begin using/producing licensed from Micron XPoint IP in their products.

June 29, 2017 | 04:12 PM - Posted by Allyn Malventano

1. Retention is far better (and cell drift lower) at lower numbers of erase cycles.

2. In modern flash, ECC is not the primary mechanism used to correct for drift. Read thresholds are adapted on-the-fly to first compensate for any drift, and then the ECC covers the remaining outliers. Adapted thresholds don't cause any additional latency.

3. The cell Z height is higher for the 3D parts, so the assumptions coming with a blanket '15nm process' statement do not apply here. IIRC, the figures at center-bottom of that keynote slide were referring to the margins, and their point was that BiCS QLC had a higher value than 15nm (planar) MLC, which is the only way they could pull something like this off in the first place.

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