Intel officially ends the era of "tick-tock" processor production

Subject: Processors | March 22, 2016 - 05:08 PM |
Tagged: Intel, tick tock, tick-tock, process technology, kaby lake

It should come as little surprise to our readers that have followed news about Kaby Lake, Intel's extension of the Skylake architecture that officially broke nearly a decade of tick-tock processor design. With tick-tock, Intel would iterate in subsequent years between a new processor microarchitecture (Sandy Bridge, Ivy Bridge, etc.) and a new process technology (45nm, 32nm, 22nm, etc.). According to this story over at, Intel's officially ending that pattern of production.

From the company's latest K-10 filing:

"We expect to lengthen the amount of time we will utilize our 14 [nanometer] and our next-generation 10 [nanometer] process technologies, further optimizing our products and process technologies while meeting the yearly market cadence for product introductions."

View Full Size

It is likely that that graphic above that showcases the changes from Tick-Tock to what is going on now isn't "to scale" and we may see more than three steps in each iteration along the way. Intel still believes that it has and will continue to have the best process technology in the world and that its processors will benefit.

Continuing further, the company indicates that "this competitive advantage will be extended in the future as the costs to build leading-edge fabrication facilities increase, and as fewer semiconductor companies will be able to leverage platform design and manufacturing."

View Full Size

Kaby Lake details leaking out...

As Scott pointed out in our discussions about this news, it might mean consumers will see advantages in longer socket compatibility going forward though I would still see this as a net-negative for technology. As process technology improvements slow down, either due to complexity or lack of competition in the market, we will see less innovation in key areas of performance and power consumption. 



March 22, 2016 | 05:18 PM - Posted by Anonymous (not verified)

Kaby Lake graphic above.

5K@30 one display, 5K@60 w/two displays.

That makes no sense.... shouldn't it be like 5K at 60 with one and @ 30 with two?

March 22, 2016 | 06:30 PM - Posted by Tim Verry

Heh weird, maybe a typo or they are combining the two 30Hz into one for some unknown reason 0.o hehe. Learning from wireless router marketing?

March 22, 2016 | 09:37 PM - Posted by Scott Michaud

Unless they mean 5k@30 with one display output, and 5K@60 with two display outputs? As in, 60 is only available in multi-link? Just speculating, though. No idea.

March 22, 2016 | 06:21 PM - Posted by Anonymous (not verified)

Well AMD optimized its Carrizo APU at 28nm and got around 30% x86 core die space savings by using its high density GPU design libraries on the layout design of Carrizo's excavator CPU cores. So there is nothing wrong with Intel having an optimization phase with its designs if it saves space without needing a node shrink. Intel really was relying on its fab process die shrinks a little too much and not paying attention to other methods to save die space or get more functionality using design layout libraries.

Intel needs to devote more time to its graphics drivers and maybe other things, before AMD's APUs on an interposer put Intel at a disadvantage for primary RAM memory bandwidth. AMD's use of high density design libraries for any 14nm CPU cores will still net AMD that around 30% space savings over CPU cores that use the standard low density design libraries for CPU core layouts. AMD will be able to fit more of its x86 Zen cores in that 14nm space and offer either smaller dies, more CPU cores, or more GPU cores to its APU graphics.

The Zen CPU core still may not be able to best Intel's offerings in IPC, but AMD will be able to get SKUs at a more affordable price points with 8 cores than Intel can offer with 4 of its cores, with AMD using optimizations like High Density design libraries, and creating APUs on an interposer with a separately fabricated Zen cores die and a separately fabricated GPU die, in addition to HBM stacks all being wired up via an interposer. That single CPU core IPC metric is becoming less important as the major graphics APIs(Vulkan/DX12) will allow for better CPU multi-core utilization, and also for more compute workloads to be moved off on the CPU cores and onto AMD's ACE units where AMD has the lead in asynchronous compute done on the GPU.

The affordable die shrink era is coming to a close, even for Intel's deep pockets, and atoms are not getting any smaller so it's time for space savings through other means like 3d die stacking, interposers, and creative circuit design layouts.

March 23, 2016 | 05:16 AM - Posted by Anonymous (not verified)

Spoken like a true amd employee , right?

March 24, 2016 | 11:02 AM - Posted by Anonymous (not verified)

All Intel CPUs in my laptops, but looking to get something with an AMD SOC if the Linux laptop OEMs will start offering the SKUs. So I do not work for any chip makers, the filthy parts suppliers that they are. AMD will have some very competative Zen SKUs and single core IPC is not as necessary, what with the software stack allowing for more compute to be offloaded to the GPU. Intel's graphcs still suck if you want to do more than just gaming or your device. AMD's and Nvidia's graphics will always be better than Intel's if you do non gaming graphics workloads with any device.

AMD, Intel, and Nvidia are merely parts suppliers to the PC/laptop/other devices OEMs, so I'm nore intrested in the technology part of thier offerings and AMDs Interposer technology has great potential to offer much better onboard graphics for AMDs Zen based APU SKUs, to go along with HBM's ability to provide massive amounts of effective bandwidth while saving on power usage, way the hell more than any standard DDR/GDDR memory over narrow memory channels. So It's about the technology, and not only about just the technology that is good for gaming, but technology that is good for non-gaming graphics uses also!

Nvidia get Your IN Hardware Async compute deficiency fixed, or you will be behind, fix your hardware's compute resources for better processor utilization. It's about the technology and who is better on the latest.

March 23, 2016 | 07:06 AM - Posted by Anonymous (not verified)

And should we expect that AMD will continue to produce massively inefficient chips that require cooling devices that can only fit inside a XL tower chassis, and consume 300% more watts for 30% less processing?

March 22, 2016 | 08:56 PM - Posted by willmore

So, this just splits out the 'optimization' step that was normally folded into Tock?

Looks like 10nm is the new 28nm.

March 22, 2016 | 11:00 PM - Posted by Anonymous (not verified)

Yes the 'optimization' step will be done over a longer time period for 10nm and below process that are going to cost more! Moore's law was more about the economics driving transistor counts doubling every 18mo to 2 years. So even At Intel's economy of scale it will take longer to fully amortize the R&D and chip fabrication costs for process shrinks 10nm and smaller. And the mobile market is where the unit sales volumes are that allow for the R&D/engineering and chip fabrication costs to be quickly amortized. But Intel's mobile market sales are not going to be at as large enough volume owning to the fact that the ARM based industries has the majority of the mobile devises market sales.

So the third party fab businesses that is supplying the needs for all that is ARM/MIPS/Other ISA based markets is seeing the sales volumes of mobile at an even larger scale than Intel saw making x86 based SKUs for the PC/laptop market. Furthermore the third party chip fabrication industry is able to spread its R&D and chip fabrication facilities costs across an entire industry of makers while Intel has its fabs mostly producing for Intel's products alone with some minor custom fabrication business between Intel and some third party makers of SOCs. The third party fab industry is also now supplying IBMs in house power8/8+ and power9 fabrication needs, along with any third party licensed from Openpower power8/power8+ and power9 needs for those power* licensees.

Intel was only to able to outspend the other chip makers for the expensive third party chip fabrication machines and the associated R&D cost that allowed Intel to outspend all others when the x86 market was the only game in town but things have changed. The chip fabrication IP/equipment that the entire world gets from the 6 companies that provide the world with the chip etching machinery and other fabrication IP. So the third party fabs are now at 14nm and already talking 7nm for some future Apple contracts.

Intel will have to keep up with a mobile market sales volume that produces many more chips for much more unit sales volumes and companies like Apple do not have to spend billions for chip fab plant upkeep or chip fab process node R&D, as the third party chip fab business will spread those development cost across the not only for Apple's SOC needs but for many other SOC makers also. Intel will have a big problem not just only from AMD's new Zen based APUs, but also from any and all of the ARM market players including from AMD's upcoming custom K12 ARMv8A running APU SKUs that will be coming online in 2017.

Intel is loosing billions on the mobile devices market and having to hide those losses by folding the its mobile devises division into a larger division to hide the bleeding on the books. The x86 market is about to become more competitive with Zen's release, and add to that from AMD's APUs and APUs on an interposer as HSA will allow for even more compute workloads to be done on AMD's APUs(x86 or ARM ISA based) for enhanced GPGPU acceleration on the APU, and AMD future Interposer based APUs! HSA is stating to pay off for AMD with both DX12 and Vulkan allowing more gaming compute workloads to be accelerated for VR on AMDs APUs. And HSA will pay off in the server market once AMD reenters that market also for x86 and ARMv8A based SKUs from AMD.

The sales volumes are just not there anymore for Intel to keep tick-tock-ing along and not able to as quickly amortize R&D and other engineering and facilities costs! So that era is over. The margins are going to have to come down for Intel also for the Cash Cow server market also from more than AMDs x86 but also ARM and power8/Power8+ and power9 from more than just IBM's power sales but third party power* sales also!

March 22, 2016 | 11:05 PM - Posted by Anonymous (not verified)

Edit: folding the its mobile devises division
To: folding its mobile devices division

April 26, 2016 | 12:20 AM - Posted by Anonymous (not verified)

I don't think "loosing" means what you think it means.

March 22, 2016 | 09:45 PM - Posted by Anonymous (not verified)

I think most people understand that a change was coming, because ever since Bulldozer Intel has really taken a backseat for the desktop CPU market and focused primarily on the mobile market

March 22, 2016 | 11:06 PM - Posted by JohnL (not verified)

I got a bad feeling about this.
The fact Intel said this means.......they are very very confident their product already beaten AMD Zen before it even out......

March 22, 2016 | 11:59 PM - Posted by han (not verified)

I got this feeling when intel blocked non-k overclocking.

March 23, 2016 | 12:06 AM - Posted by Pixy Misa (not verified)

Or they're simply stuck with the laws of physics and can't iterate as fast as they used to.

March 23, 2016 | 07:00 AM - Posted by Gunbuster

Intel has an 18 core Xeon they could rebrand to desktop anytime they want. Or they could use a 6 core, or the 8 core, or the 10 core, 12 core, 14 core, or 16 core. They literally just need to change the laser etcher template from Xeon to Core iwhatever.

March 22, 2016 | 11:15 PM - Posted by Goofus Maximus (not verified)

From Tick-Tock to Tic-Tac-Toe! The new rhythm by which they devise their devices...

March 22, 2016 | 11:42 PM - Posted by Anonymous (not verified)

Higher and higher clock speeds met their end to multiple cores. Now that shrinking process is getting down to the number of atoms you can count I predict adding more cores will also come to an end. Well an end as we know it. I think we will be seeing more of the system on chip and/or cores evolving into processing units where you no longer count a CPU by its cores.

March 23, 2016 | 12:03 AM - Posted by zgradt

Oh, *now* it's official. Sounds like they're still pretending that Broadwell doesn't exist.

March 23, 2016 | 05:05 AM - Posted by Anonymous (not verified)

This is quite big. Do you guys plan to investigate as to why exactly Intel took this decision? I doubt its anything to do with the limits of their own technology.

March 23, 2016 | 09:10 AM - Posted by Anonymous (not verified)

It is pretty obvious that there are yield issues at these smaller process nodes, so I expect it definitely has to do with the limits of their own technology. In fact it has to do with some basic physical limitations. They are now trying to make 14 nm features with 193 nm light. It is amazing that they managed to stretch it this far. Billions of dollars are being poured into research, but I don't think they have a clear path to a solution yet. It is pretty basic science that exponential functions can not be maintained indefinitely, so CMOS scaling will come to an end. They still may be able to make improvements to the process tech without going smaller.

April 26, 2016 | 12:24 AM - Posted by Anonymous (not verified)

How do you know how expensive that specific research is? How do you know it is poured?

March 23, 2016 | 12:32 PM - Posted by Drazen (not verified)

We must be aware how complicated is to switch from 10nm to, let's say, 7nm. Switching from 7 to 5 will be much more complicated. At this sizes we start talking of few atom distances and nobody knows what is waiting there.
On other side chip must be verified and this is very complicated and takes ages to simulate. Even a small change will require weeks to verify.
But shrinking also makes new problems on software side. Today most of software is not optimized and situation will get worst.

Post new comment

The content of this field is kept private and will not be shown publicly.
  • Lines and paragraphs break automatically.
  • Allowed HTML tags: <a> <em> <strong> <cite> <code> <ul> <ol> <li> <dl> <dt> <dd> <blockquote><p><br>
  • Web page addresses and e-mail addresses turn into links automatically.

More information about formatting options

This question is for testing whether you are a human visitor and to prevent automated spam submissions.