AMD Shows Off Zen 2-Based EPYC "Rome" Server Processor
Subject: Processors | November 7, 2018 - 11:00 PM | Tim Verry
Tagged: Zen 2, rome, PCI-e 4, Infinity Fabric, EPYC, ddr4, amd, 7nm
In addition to AMD's reveal of 7nm GPUs used in its Radeon Instinct MI60 and MI50 graphics cards (aimed at machine learning and other HPC acceleration), the company teased a few morsels of information on its 7nm CPUs. Specifically, AMD teased attendees of its New Horizon event with information on its 7nm "Rome" EPYC processors based on the new Zen 2 architecture.
Tom's Hardware spotted the upcoming Epyc processor at AMD's New Horizon event.
The codenamed "Rome" EPYC processors will utilize a MCM design like its EPYC and Threadripper predecessors, but increases the number of CPU dies from four to eight (with each chiplet containing eight cores with two CCXs) and adds a new 14nm I/O die that sits in the center of processor that consolidates memory and I/O channels to help even-out the latency among all the cores of the various dies. This new approach allows each chip to directly access up to eight channels of DDR4 memory (up to 4TB) and will no longer have to send requests to neighboring dies connected to memory which was the case with, for example, Threadripper 2. The I/O die is speculated by TechPowerUp to also be responsible for other I/O duties such as PCI-E 4.0 and the PCH communication duties previously integrated into each die.
"Rome" EPYC processors with up to 64 cores (128 threads) are expected to launch next year with AMD already sampling processors to its biggest enterprise clients. The new Zen 2-based processors should work with existing Naples and future Milan server platforms. EPYC will feature from four to up to eight 7nm Zen 2 dies connected via Infinity Fabric to a 14nm I/O die.
AMD CEO Lisa Su holding up "Rome" EPYC CPU during press conference earlier this year.
The new 7nm Zen 2 CPU dies are much smaller than the dies of previous generation parts (even 12nm Zen+). AMD has not provided full details on the changes it has made with the new Zen 2 architecutre, but it has apparently heavily tweaked the front end operations (branch prediction, pre-fetching) and increased cache sizes as well as doubling the size of the FPUs to 256-bit. The architectural improvements alogn with the die shrink should allow AMD to show off some respectable IPC improvements and I am interested to see details and how Zen 2 will shake out.