AMD Ryzen Mobile Picasso APUs Spotted in Benchmark Results

Subject: Processors | December 19, 2018 - 08:47 PM |
Tagged: Zen+, ryzen mobile, ryzen, rumor, picasso, geekbench, amd

Twitter user APISAK is at it again with more hardware leaks, and this time the rumors surround AMD's next generation mobile 3000U-series "Picasso" APUs which will replace Raven Ridge in 2019. The new APUs were reportedly spotted by APISAK (@TUM_APISAK on Twitter) as reported by Hexus in two HP laptops in 14" and 17" form factors and offer power efficiency and performance improvements over Raven Ridge's CPU cores along with Vega-based graphics. Searching around online and parsing the various conflicting rumors and speculation on Picasso, I think it is most likely that Picasso is 12nm and utilizes Zen+ CPU cores though it remains to be seen how true that is.

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Based on previous roadmaps, AMD's APUs have trailed the desktop CPUs in process technology and architecture instead opting to refine the previous generation for mobile rather than operating at its bleeding edge so while 2019 will see Zen 2 architecture-based CPUs and GPUs built on 7nm, APUs in 2019 are likely to stick with 12nm and Zen+ tuned for a mobile power envelope with tweaks to SenseMI and technology like mobile XFR and dynamic power delivery.

In any event, Picasso APUs are rumored to include the Ryzen 3 3200U, Ryzen 3 3300U, and Ryzen 5 3500U based on Geekbench results pages as well as the low-end [Athlon?] 3000U and the high-end Ryzen 5 3700U - according to the source. The 3000U and 3700U are known in name only, but the middle-tier APUs have a bit more information available thanks to Geekbench. The Ryzen 3 3200U is a dual core (four thread) part while the Ryzen 3 3300U and Ryzen 5 3500U are quad core (eight thread) CPUs. All Picasso APUs are rumored to use Vega-based graphics. The dual core APU has the highest base clock at 2.6 Ghz while the 3300U and 3500U start at 2.1 GHz. The Ryzen 5 3700U allegedly clocks from 2.2 GHz to 3.8 GHz and likely has the highest boost clock of the bunch. The parts use the FP5 mobile socket.

Picasso APU Geekbench scores based on HP Laptop 17-ca1xxx except 3200U Compute which is from HP Laptop 14-cm1xxx. Carrizo APU scores based on HP Pavilion. The i5-8359U CPU scores are from. HP Elitebook X360 and Compute score from Dell Latitude 7490.
  Athlon(?) 3000U Ryzen 3 3200U Ryzen 3 3300U Ryzen 5 3500U Ryzen 5 3700U A10-8700P (Carrizo) Intel Core i5-8359U
Cores / Threads ? 2 / 4 4 / 4 4 / 8 4 / 8 2 / 4 4 / 8
Base / Boost Clocks ? 2.6 / ? GHz 2.1 / ? GHz 2.1 / ? GHz 2.2 / 3.8 GHz 1.8 / 3.19 GHz 1.9 / 3.59 GHz
Cache ? 4 MB 4 MB 4 MB 4 MB 2 MB 6 MB
Graphics Vega Vega 3 6 CU (920 MHz) Vega 6 6 CU (1.2 GHz) Vega 8 8 CU (1.2 GHz) Vega R6 6 CUs (GCN 1.2) UHD 620 24 CUs (1.1 GHz)
Socket FP5/AM4 FP5/AM4 FP5/AM4 FP5/AM4 FP5/AM4 FP4 1356 FCBGA
Geekbench Single Core ? 3467 3654 3870 ? 2113 4215
Geekbench Multi Core ? 6735 9686 11284 ? 4328 12768
Geekbench Graphics ? 23698 26540 31947 ? 20009 16279

Looking at the Geekbench results (which you should take with a grain of salt and as just an approximation because final scores would depend on the platform, cooling, and how it ends up clocking within its power envelope) it seems that AMD may have a decent chip on its hands that improves the performance over Raven Ridge a bit and significantly over its older Excavator-based pre-Zen designs. A cursory comparison with Kaby Lake shows that AMD is not quite to par in CPU performance (particularly per core but it comes close in multi-core) but offers notably better compute / GPU performance thanks to the Vega graphics. It seems that AMD is closing the gap at least with Zen+.

I am remaining skeptical but optimistic about AMD's Picasso APUs. I am looking forward to more information on the new chips and the devices that will use them. I am hoping that my educated guess is correct with regard to Picasso being 12nm Zen+ or better as rumor is mainly that Picasso is a Raven Ridge successor that offers power and performance tweaks without going into further detail. I expect more information on Picasso (APU) and Matisse (CPU) to come out as soon as next month at CES 2019.

What are your thoughts on Picasso?

Source: Hexus

December 20, 2018 | 09:11 AM - Posted by Peter Connell (not verified)

"it comes close in multi-core) but offers notably better compute / GPU performance thanks to the Vega graphics. It seems that AMD is closing the gap at least with Zen+."

What gap? Your condescending fantasies about the markets real priorities belong in an Intel brochure.

December 20, 2018 | 12:25 PM - Posted by AMDsGotMoreTimeAndResourcesToTargetSpecificMarkets (not verified)

The CPU single core IPC gap with Intel is still there but Vega Graphics is already much better than Intel's Integrated graphics currently.

I see this as AMD moving all of its remaining consumer market Globalfoundres production over to 12nm and off of 14 just to get the better 12nm transistor tweaks that are what is responsible for the power savings and/or increased clocks. I'm sure by the back to school season 2019 that AMD would have APUs at 7nm but any incremental improvment would be welcome. Even at 12nm, if true for Picasso, AMD could still produce an improved 12nm stepping and GF's 12 process will be more mature with better all around binning available.

The Professional Zen-1/Epyc 14nm production will still be ongoing 2 years from now as will the 14nm Rome 1/O die production because once a server CPU design is Vetted and Certified all changes are mostly frozen with any redically new changes forcing the new design to have to be re-vetted and re-certified. So GF will be still producing Zen-1 Zeppelin Dies for the Epyc/Naples market for a good many years.

So for the Zen-1/Zeppelin Die Epyc/Naples it's only going to get errata fixes and new speppings and some new SKUs with higher clocks as the result of binning improvments but the server market demands and gets extended product availabllity and that means guaranteed parts availbility for at least 5+ years on any Epyc/Naples branded parts. Ditto for any Ryzen Pro Branded parts that go into OEM business grade PCs/Laptops where enterprises order 10s of thousands of PCs/Laptops of the same design and expect that spare parts be made available for at least 5+ years also.

If you take the time to properly research GF's 12nm process node you will see it's not necessary to have a shrink to get transistor performance improvements if the transistor design is tweaked and the diffusion recipe improved also.

AMD could have also opted to bring the 14nm designs/layouts directly over to GF's 12nm node and kept the same layout libreries that where used at 14nm with no area savings for their Ryzen 2000 series in order to save time and still get the benifit of that 12nm transistor design tweaking that GF did (1). GF kept the same metal layer pitch on its 12nm node for just such a reason and that's was to make it easy for its current 14nm clients to move over to 12nm and get the transistor improvements.

Now if you read the Wikichip Fuse article you will see that GF's 12nm process allows any client to remaing on a 9.5T layout library(Same As the 14nm 9.5T) but still get the 12nm process node's transistor tweaking that's responsible for better power usage metrics or will allow for higher clocks at no extra power savings. GF also certified the 12nm node for with a new denser 7.5T library that has a smaller Cell size that is ready made for achieving denser transistor packing at reduced performance metrics for mobile designs that are clocked lower anyways to meet mobile thermal form factor constraints.

So AMD has the option on Mobile Raven Ridge on GF's 12nm node to go with those 7.5T layout's 10 fins per cell instead of the 9.5T layout's 12 fins per cell. Less fins per cell means less space required but that also means the design can not use as many 3 fin transistor designs and has to use more 2 fin transistor designs with less desirable performance characteristics i.e. higher clock speeds are not as obtainable compared to transistors that use the less dense 9.5T libraries with 3 fin transistors. So AMD if it makes us of 12nm for Picasso and uses the 7.5T libraries could net some space savings for more GPU resources or other feature improvments on any Picasso/Mobile.

There is also the possibility that even the Zen-2 micro-arch could have been laid out at 12nm/7.5T also in addition to being laid out on 7nm for the Epyc/Rome server chips. Or maybe this Picasso is in fact some Zen-2 mobile Variant Micro-Arch that's maybe lacking some feature parity with the server/desktop Zen-2 designs. Intel has low power x86 lines of x86 micro-arch based CPUs as has AMD with its Jaguar cores.

AMD's got more time and resources to begin to target mobile Zen generational designs that are specifically for the mobile low power mobile market. So that may be taking place now that AMD has more breathing room and resources to target specific CPU market segements.

(1)

"VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP"

https://fuse.wikichip.org/news/1497/vlsi-2018-globalfoundries-12nm-leadi...

December 21, 2018 | 05:22 AM - Posted by lexx

Wall of text lol

Dislikes the duel core model ( as that means both systems will come with that one because it'll be the cheapest hey at least it won't be as bad as the E CPUs as thus is ryzen)

January 10, 2019 | 05:34 AM - Posted by MarkChambers

I am not expecting something extreme modern of these.

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