AMD Compares 1x 32-Core EPYC to 2x 12-Core Xeon E5s

Subject: Processors | May 17, 2017 - 04:05 AM |
Tagged: amd, EPYC, 32 core, 64 thread, Intel, Broadwell-E, xeon

AMD has formally announced their EPYC CPUs. While Sebastian covered the product specifications, AMD has also released performance claims against a pair of Intel’s Broadwell-E Xeons. While Intel’s E5-2650 v4 processors have an MSRP of around $1170 USD, each, we don’t know how that price will compare to AMD’s offering. At first glance, pitting thirty two cores against two twelve-core chips seems a bit unfair, although it could end up being a very fair comparison if the prices align.

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Image Credit: Patrick Moorhead

Patrick Moorhead, who was at the event, tweeted out photos of a benchmark where Ubuntu was compiled over GCC. It looks like EPYC completed in just 33.7s while the Broadwell-E chip took 37.2s (making AMD’s part ~9.5% faster). While this, again, stems from having a third more cores, this depends on how much AMD is going to charge you for them, versus Intel’s current pricing structure.

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Image Credit: Patrick Moorhead

This one chip also has 128 PCIe lanes, rather than Intel’s 80 total lanes spread across two chips.

May 17, 2017 | 06:41 AM - Posted by Hakuren

It shapes to be totally crazy (in a positive way) chip.

Seems like times of sitting on a back side while cutting the coupons and milking (monopolizing) the market are truly over for Intel. Even if only short term (Chipzilla is still a behemoth) it will do much good to the market across all spectrum of customers.

Holy cow 128 lanes. That's 7x16 slots with still 16 lanes left without any PLX shenanigans. Just wow.

May 17, 2017 | 09:12 AM - Posted by LazarusIV

Yeah, you hit the nail on the head. I feel like the cores and performance (presumably for a great price) are good, but the real is the platform itself. All of those DIMMs and PCIe lanes built into the platform itself is just astounding. I'm so excited to see how the desktop and enterprise market changes over the next couple of years, and I am anxiously awaiting mobile Ryzen!

May 17, 2017 | 10:00 AM - Posted by zgradt

Man, who's in charge of handing out names at AMD? EPYC vs. E5-2650 v4. Threadripper vs Core i9. Ryzen vs Core i7/i5.

May 17, 2017 | 11:32 AM - Posted by Srsbsns

If you look at both of these last two AMD CPU articles you will notice negative keywords peppered throughout. Combine this with "its just not fair" and no wonder people are losing faith in this site providing a balanced "Perspective".

May 17, 2017 | 07:30 PM - Posted by CNote

I didn't find their Ryzen coverage any more negative than any other site. Hell they are shilling for AMD right now...

May 17, 2017 | 01:46 PM - Posted by StephanS

The AMD presentation had this acronym spoken many times : TCO

The other advantages with the 32 core single socket, beside higher performance and more IO:
- smaller
- lower power

May 17, 2017 | 08:30 PM - Posted by FakeGamerGuy

Can't forget how much cheaper single-socket boards tend to be compared to dual-socket.

May 17, 2017 | 08:37 PM - Posted by PixyMisa

Unifying the PCIe and Infinity Fabric pins was a stroke of genius. With 32 cores being enough for many applications, it means a 1S system has all 128 lanes available for IO, three times that of a 1S Intel server.

As you say, it comes down to pricing now. These shouldn't be hugely expensive chips to produce since they're just four Zen dies on an MCM. I expect 2H 2017 will be a big deal for AMD.

May 18, 2017 | 01:05 PM - Posted by James

Intel does a similar thing with their HSIO lanes which can be reconfigured, although in a somewhat limited manner. I really want to know how exactly their interconnect works. I found some stuff on pci express advanced switching that seems similar. It looks like a standard that died a long time ago though; not sure why. Perhaps limited industry support. It isn't in Intel's best interest to let just anyone attach cache coherent accelerators to their processors.

I don't think we even know exactly how the 4 die in the MCM are connected. If they use full 32 lane links between each, then they can get remote memory bandwidth close to local bandwidth. It would be more latency than fully connected with narrower links though. Not sure if fully connected is worth it. The chips have a lot of cache and the interconnect operates probably faster than 8 GHz. With how short the traces will be on package, they could probably operate the links at even higher than pcie 3 speeds.