TSMC Will Begin Mass Production of Enhanced 7nm Node Using EUV In March, 5nm to Follow

Subject: General Tech | February 23, 2019 - 03:08 PM |
Tagged: TSMC, lithography, euv, asml, 7nm, 5nm

According to Hexus, chip manufacturing giant TSMC will begin mass production of its enhanced 7nm process node as soon as next month. The new "CLN7FF+, N7+" mode incorporates limited use of EUV (extreme ultraviolet lithography) on four non-critical layers using specialized equipment from ASML to offer 20% higher transistor density and between six to twelve percent lower power consumption at the same complexity/frequency. Those numbers are versus TSMC's current 7nm process node (CLN7FF, N7) which uses DUV (deep ultraviolet lithography) with ArF (Argon Fluoride) excimer lasers.

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TSMC is reportedly buying up slightly more than half of ASML's production of EUV equipment for 2019 with the chip maker reserving 18 of the 30 EUV units that will ship this year. It will use the ASML Twinscan NXE step and scan machines to produce its enhanced 7nm node and allow TSMC to familiarize themselves with the technology and dial it in for use with its upcoming 5nm node (and beyond) which will more heavily incorporate EUV with it being used on up to 14 layers of the 5nm process node manufacturing. AnandTech reports that the 5nm EUV node will bring 1.8-times the transistor density (45% area reduction) of the non-EUV 7nm node along with either 20% less power usage or 15% more performance at the same chip complexity and frequency.

Interestingly, while 7nm production accounted for roughly 9% of TSMC's output in 2018, it will reportedly be up to a quarter of all TSMC's chip shipments in 2019.

Mass production of the 7nm EUV node will begin as soon as March with risk production of 5nm chips slated to being in April with the first chip designs being taped out within the first half of the year. Volume production of 5nm chips is not expected until the first half of 2020, however, though that would put it just in time for AMD's Zen 2+ architecture. Of course, AMD, Apple, HiSilicon, and Xilinx are TSMC's big customers for the current 7nm node (especially AMD who is using TSMC for its 7nm CPU and GPU orders), and Huawei / HiSilicon may well be TSMC's first customer for the EUV incorporating CLN7FF+, N7+ node. 

With GlobalFoundries backing off of leading-edge process techs and shelving 7nm, Intel and Samsung are TSMC's competition in this extremely complicated and expensive space. 2020 and beyond are going to be very interesting as EUV production ramps up and is pushed as far as it can go to bring process technologies as close to the theoretical limits that the market will bear. I think we still have a good while left for process shrinks, with some of these lower node numbers being attributed to marketing (with some elements being that small but depending on what and how they measure these nodes) but it is definitely going to get expensive and I am curious who will continue on and carry the ball to the traditional manufacturing process finish line or if we will need some other exotic materials or way of computing paradigm shift to happen before we even attempt to get there simply due to unrealistic R&D and other costs not making it worth it enough for even the big players to pursue.

In talking with Josh Walrath, he clarified that EUV does not, by itself, offer performance enhancements, but it does cut down on exposures/patterning and reduces the steps where things can go wrong which can lead to improved yields when implemented correctly. Using extreme ultraviolet lithography isn't a magic bullet though, as the fabrication equipment is expensive and uses a lot of power driving up manufacturing costs. TSMC is using EUV on its N7+ node to get "tighter metal pitch" and more density along with lower power consumption. Performance improvements are still unknown  at this point (to the public, anyway), but as Mr. Walrath said performance isn't going to increase simply from moving to EUV. When moving to 5nm, TSMC does claim performance improvements, but most of those gains are likely attributed to the much higher density of the resulting chips.  Using EUV to get yields up at that small of a node is likely the biggest reason for utilizing EUV to get enough useable wafer and dies per wafer. TSMC must believe that the costs [of EUV] versus trying to do it [5nm] without working in EUV into the processis worth it. Stay tuned to this week's PC Perspective podcast if you are interested in additional thoughts from JoshTekk and the team (or check out our Discord server).

What are your thoughts?

Source: Hexus

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February 23, 2019 | 04:57 PM - Posted by bobhumplick (not verified)

the EUV isnt being used on the whole chip. according to this its just for the metal layers. i woudlnt be surprised if it has no scaling. you have to do the whole chip on EUV to really see any difference and even then it wont be higher performance or less power. the goal will be better yields and this first step wont do much for yields either. you need the whole chip to be using EUV for that. if you still have quad patterning for the rest of the layers then you still have yield issues.

i actually thought it was just going to be for the backend with vias and connectors having EUV. similar to the way amd's current chips have a 14nm backend but are really 20nm on the actual logic. but if some of the actual logic is being made on EUV then thats a bit more advanced.

bottom line is this move to use EUV will just get them some experience with it and help transition things a bit more smooth. you will need total EUV which will allow single or at least dual patterning for yields to improve which is what is limiting large dies.

thats why amd have went to mulitchip partly and also why nvidia arent using 7nm for gpus. you just cant make the dies large enough without have huge yield issues. and of course when yields get better there will be less need for amd's mutlichip design. at least it wont have any great advantage for someobdy that does a lot of volume like intel. monolithic dies will have good enough yields for 7nmtsmc (10nm intel) and probalby 5nm tsmc (7nm intel) because single and dual patterning will be enough for them.

amd however make many less chips so the multichip approach will still help them because they wont have the larger volume of chips to bin from like intel does. they can sink the lower qualtiy dies into consoles and lower end cpus and use the best for server\high end cpus.

of coruse there will be challenges with EUV and the power required is astronomical. and the improves for each node shrink will be greatly diminished and costs for new nodes will go up to the point that shrinking a certain amount of cores down wont actualy make them cheaper. possibly more expensive. the only real benefit will be power savings and that will be less than we are used to. its already happening with tsmc's 7nm compared to intels 14nm (which is the same size as tsmc's 10nm). the only real benefit of tsmc;s new node compared to intels old node is power.

intel could push through and take the hit on yields and use multichip. but it makes much less sense to do the whole line that way. instead they will do mobile on 10nm for the power savings (they are smaller dies anyway) and use 14nm for everything else for awhile. it actually makes pretty good business sense to do this. till EUV comes smaller nodes dont offer much for the cost that goes into them

people are hat

February 23, 2019 | 09:31 PM - Posted by RealityIsLostOnGamersOutInLaLaLAsEUVimprovesTimeToMarket (not verified)

So what if TSMC is only using EUV for the BEOL(Metal Layers) because that's still going to reduce some mask steps in the process so that's going to improve wafer production volume by shortening the time from wafer start to wafer completion. So any EUV used in the overall process is good and I'd rather TSMC take their time moving the production of the FEOL(Transistor layers) over to EUV.

And EUV on metal layers of finer Pitch metrics is necessary if TSMC does not want to lose any space savings of the smaller 5nm gate sizes. So simply dismissing EUV out of hand without taking the time to read and learn is not going to win over any arguments.

There are things called design libraries(9.5T and 7.5T for example) that have various amounts of Fins per Cell and transistor layer fin pitches! And with gate pitches that are getting smaller the metal layer pitches have to get smaller also. And smaller metal layer pitches will be necessary to accomodate the transistor sizes or any space savings will be lost. So depending on the design libraries that are going to be certified for TSMC 5nm production the smaller metal layer pitch options will become a much easier task using EUV and simpler mask sets.

There is much sharper imaging using EUV so even for metal layers that translates into less room for any variances in the imaging fidelity as the fab processes becomes smaller. An acceptable metal layer inaging variance at a larger node may become unacceptable at a smaller node so EUV used anywhere in the process for better fidelity of the metal layers definitely justifies the use of EUV.

There is a direct relationship to the numbers of fabrication steps required to the numbers of errors introduced into the production process and the less steps the less chances for defects to occur.

EUV is also going to shorten the turnaround times if any processor design validation process misses something and that's discorved only after the engineering samples arrive Back from the fab. So if design flaw/s are found that's a shorter delay in waiting for the new fixes to come back from the fab's engineering sample line. Shorter turnaround times save overall time to market and time really is money especially in the fab business for both the fab and its clients.

February 23, 2019 | 06:03 PM - Posted by chipman (not verified)

TSMC pretends to mass produce in 7 nm via EUV but not a word about any R E A L product using this technology... that sounds like dumb M A R K E T I N G!

February 24, 2019 | 11:11 AM - Posted by Eric Klien (not verified)

"TSMC pretends to mass produce in 7 nm via EUV but not a word about any R E A L product using this technology... that sounds like dumb M A R K E T I N G!" Their big 7nm with EUV product for 2019 is Apple's A13 chip. Likewise, last year their big 7nm product was an Apple chip and same with next year for their 5nm with EUV product.

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