Synopsys Presents USB 3.2 Demo

Subject: General Tech | May 28, 2018 - 10:32 PM |
Tagged: usb 3.2, usb, synposys, FPGA

Synopsys has just published a video on YouTube where they connect two bonded lanes over a standard Type-C cable. This was accomplished with a host USB 3.2 controller embodied by an FPGA board. The device controller is the same hardware that was configured to be seen by the pair as a USB device.

In case you're wondering, the demo happens at around 1:48. Blink and it's over.

From a practical standpoint, USB 3.2 is still some time away, and a factor of 2 speed-up is not too large considering the amount of bandwidth that USB 3.1 already provides. That said, more bandwidth is always better, especially when you’re running in industrial or other professional workloads, and especially in places where Thunderbolt has marketshare.

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May 29, 2018 | 01:32 AM - Posted by PixyMisa

I've been waiting for this ever since the USB-C pinout was revealed. The next thing I'd like to see is SATA being replaced by USB.

May 29, 2018 | 05:57 AM - Posted by dub (not verified)

I'm all about protocol simplification and SSDs could certainly in return especially for the ability to treat external drives as first class citizens for stuff like booting Windows, but I don't see it happening. There's just stupid momentum behind SATA as the boring storage workhorse protocol of choice and messy tech/econ challenges blocking a migration.

a) USB3.1g2 (10Gbit) is the only version with any advantage over SATA 6Gbit and it's still rare as hell with 1-2 ports at best even on high end new mobos.

b) Even on high end new mobos the connectors are external

c) That means there's precisely zero market space for native USB HDDs, and significant expense in replacing tested and true SATA. Gotta account for the eccentricities of each protocol including I believe higher latency on USB, plus build up IP to enable stuff like USB RAID (which IMHO should just be software-based ie Storage Spaces these days but still...)

d) Mobo/chipset makers are already building up support for the known next gen standards, M.2 and U.2. The last thing they want is needing more ports on already-cramped mobos, especially when there's no demand for the new ports.

May 29, 2018 | 08:57 AM - Posted by PixyMisa

U.2 and M.2 are fine, but you don't get many of them. SATA Express is a train wreck, and SATA seems to be a dead end. USB-C is the logical replacement.

May 29, 2018 | 12:08 PM - Posted by Paul A. Mitchell (not verified)

> ability to treat external drives as first class citizens for stuff like booting Windows


Along those same lines, I believe it would also be feasible for Windows to boot from a software OS-defined RAID array, if the necessary files were pre-written to a USB thumb drive.

Yes, this ability will also require modifications to BIOS/UEFI subsystems, in order to tell the system where to find those files.

With the proliferation of multi-core CPUs, the need for dedicated Input-Output Processors ("IOP") on PCIe add-in cards appears to be waning. Idle cores in modern CPUs can do the work of dedicated IOPs.

This realization was one of the motivations for "quad" M.2 cards like the ASRock Ultra Quad M.2 and the ASUS Hyper M.2 x16 cards, which easily surpass the MAX HEADROOM imposed by Intel's DMI 4.0 link.

Maybe a future version of Windows will make it possible to boot a future OS from a software-defined RAID array.

With the advent of PCIe 4.0 motherboards, PCIe storage will be positioned to exploit the enormous bandwidth that comes with a 16G transmission clock.

Mass storage is now approaching raw speeds that are comparable to raw DRAM speeds! This is a very interesting development, across the board.

May 29, 2018 | 12:10 PM - Posted by Paul A. Mitchell (not verified)

clerical correction:

DMI 4.0 link
should be
DMI 3.0 link

sorry for the typo

May 29, 2018 | 08:53 AM - Posted by LinksOfTwoFer20GbsTAB (not verified)

USB 3.2 is just 2, USB 3.1 Gen 2(10 Gb/s) channels over Type C plug's USB channel and the same Type C Plug's alt channel wires so there is not much new as far as the IP is concerned. So those 2(USB 3.1 10Gb/s) channels are link bonded/link aggregated to provide the 20 GB/s of total aggregate bandwidth. So instead of going faster the USB-IF folks whent wider with 2, 3.1 channels/lanes instead of one faster channel and the USB Type C plug standard already provides the extra wires needed.

The big problem with Laptops is not haveing enough PCIe links to spare for things like TB3 and USB 3.1 Gen 2/3.2 bandwidth needs. Laptops are the first devices that need to get PCIe 4.0 ablity in order to have enough connectivity/bandwith to service all these new higher bandwidth TB3/USB generations of controllers.

I would really be nice if TB3 could be link bonded/link aggregated and provide even more bandwidth for external GPU enclosures. But that mush bandwidth will have to wait for PCIe 4.0 and later.

I hope that Synposys starts building TB3 controllers of its own as they are already providing plent of IP to the SOC/CPU interface market(25G SERDES PHY, PCIe 3.1/SATA/Other PHY) etc.

May 29, 2018 | 11:50 AM - Posted by Paul A. Mitchell (not verified)

I truly LUV this debate, in part because it helps the industry maintain awareness of practical opportunities that can be exploited without too much additional R&D.

Take, as one example, 12G SAS. On the margin, it was feasible to up the clock rate. However, that one change could have also exploited the extra efficiency of the 128b/130b jumbo frame that is a feature of the PCIe 3.0 specification.

USB 3.1 did exploit that extra efficiency by supporting a 128b/132b jumbo frame.

Please permit me to re-introduce the enormous advantages that obtained from adherence to the principles of Plug-and-Play:

At the Storage Developer Conference back in 2012, we suggested that clock rates should be variable, and that storage subsystems should "sync" with chipsets.

Happily, M.2 NVMe devices did that by extending the PCIe 3.0 jumbo frame and 8G clock rate over the sockets, and U.2 cables, that accommodate those devices.

If anything should be done to improve SATA "on the margin" (i.e. without disrupting that ubiquitous ecosystem), I still advocate the following incremental improvements:

(a) support the PCIe 128b/130b jumbo frame;

(b) sync the SATA clock rate with PCIe 3.0 chipsets;

(c) sync the SATA clock rate with future PCIe 4.0 chipsets.

Take note of how most modern 6G SSDs remain plug-compatible with 3G ports on older motherboards. So, the industry is already supporting auto-detection in that manner.

It should not be too difficult for future "SATA-IV" devices to exploit power-on arbitration which permits those devices to negotiate these key parameters with the host:

If the host clock is still running at 6G, then adjust.

If the host frame is still the 8b/10b legacy frame, then adjust.

If the device clock is 8G but the host supports 12G, then adjust.

And so on.

This type of arbitration was always necessary to achieve the valuable goals of Plug-and-Play.

Hope this helps.

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