Podcast #502 - Computex coverage and more!

Subject: General Tech | June 7, 2018 - 11:50 AM |
Tagged: xTend, xps, video, Vega, Threadripper, Snapdragon 850, seasonic, scmd, ROG, qualcomm, podcast, Optane, nvidia, microsoft, logitech, Killer Wireless, Isaac, InWin, Intel, i7-8086k, git, fortnite, EPYC, dell, crystal, corsair, CaseKing, asus, aorus, amd, 7nm

PC Perspective Podcast #502 - 06/07/18

Join us this week for discussion on Computex and more!

You can subscribe to us through iTunes and you can still access it directly through the RSS page HERE.

The URL for the podcast is: http://pcper.com/podcast - Share with your friends!

Hosts: Ryan Shrout, Jeremy Hellstrom, Josh Walrath, Ken Addison

Peanut Gallery: Alex Lustenberg

Program length: 1:45:27

Podcast topics of discussion:
  1. Week in Review:
  2. News items of interest:
    1. 1:00:40 ASUS all the things
  3. Picks of the Week:
  4. Closing/outro
 
Source:

June 7, 2018 | 05:38 PM - Posted by ReallyMoreCoresThisTime (not verified)

2018's Computex will become known as the Computex of Really More Cores and consumer core counts at up to 32 cores should be enough for a good while. TR2 is not getting any new MB socket and maybe in 2019 AMD could at least offer some new TR MB variant with at least 6 memory channels and more PCIe lanes. I just think that maybe MB makers could somehow find a way to make use of those extra avialable on die TR2 PCIe 3.0 connectivity but that depends on the pins being made avilable on the TR2 SKUs with 4 active DIEs.

At least the MB makers would not need any expensive Plex chips to get more PCIe lanes what with 64 lanes of unused PCIe lanes available on those 2 out of 4 dies that are not using any PCIe 3.0 connectivity of their allotment of Lanes on the TR2(4 die variants). If that is in fact how AMD has broken up the PCIe lane allotments among the dies for TR2 to maintain backward compatability with the TR4 socket pinouts. But maybe there is some internal Infinity Fabric cross-bar switching that allows for remapping PCIe lanes among the 4 available DIEs without having to rearrange the socket's physical pinout.

I hope that at least for the 24 core TR2 variants that AMD decides to allow the available cores to retain the maximum L3 cache allotment because the addtitonal 2 active dies will not have their memory controllers active so the more L3 cache the Better for the limited available IF/memory controller traffic bandwidth.

When the next version of Epyc(Epyc2) arrives, Epyc/Rome, that's going to have even more cache and cores with an even larger L3/other cache per core ratio that will be making use of the Zen 2 Micro-Arch on 7nm. So once TR3 becomes available that makes use of the same Zen2/Zeppelin DIEs maybe there can be some newer Threadripper Socket and hopefully PCIe 4.0/5.0 or just some more PCIe 3.0 lanes for consumer TR.

If Zen+ was never intended to be used for Epyc SKUs then AMD could have removed a good part of that excess server functionaliy from any Zen+ design. So really now that TR2 is announced AMD really needs to make with the white papers that explain more about just what may be different on the Zen+ Die's non-core functionality on those Zen+ DIEs. There are probably a good amount of differences between any Zen+ Die compared to the original Zen/Zeppelin Die that was used across both server and consumer platforms.

June 8, 2018 | 04:20 AM - Posted by Johan Steyn (not verified)

You seriously are defending Intel too much. They messed up seriously. It is inexcusable. Doing this should in no way be excused, ever.

June 8, 2018 | 04:32 AM - Posted by Johan Steyn (not verified)

Two dies of the TR2 are not connected to memory. We will see how that impacts performance. They have to work through infinity fabric to the other dies' controllers.

TR2 has four channels. The HEDT PC's are budget compared to server parts. If that was not the case, a buyer could just go and buy a server. The HEDT is a drop in specs to save money. That is not what Intel did. They just took a Xeon. Why not then just buy a Xeon? Why then not just buy an Epyc 64 core instead of the 28 core? It will probably be cheaper as well.

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