Honey, I shrunk the silicon

Subject: General Tech | June 5, 2017 - 12:41 PM |
Tagged: IBM, global foundries, Samsung, 5nm, 3nm. eulv, GAAFET

Extreme Ultraviolet Lithography has been the hope for reducing process size below the current size but it had not been used to create a successful 5nm chip, until now.  IBM, Samsung and GLOBALFOUNDRIES have succeeded in producing a chip using IBM's gate-all-around transistors, which will be known as GAAFETs and will likely replace the current tri-gate FinFETs used today.  A GAAFET resembles a FinFET rotated 90 degrees so that the channels run horizontally, stacked three layers high with gates filling in the gaps, hence the name chosen. 

Density will go up, this process will fit 30 billion transistors in a 50mm2 chip, 50% more than the previous best commercial process and performance can be increased by 40% at the same power as our current chips or offer the same performance while consuming 75% less power.  Ars Technica delves into the technology required to make GAAFETs and more of the potential in their article.

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"IBM, working with Samsung and GlobalFoundries, has unveiled the world's first 5nm silicon chip. Beyond the usual power, performance, and density improvement from moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA) transistors, and the first real use of extreme ultraviolet (EUV) lithography."

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Source: Ars Technica

June 5, 2017 | 02:40 PM - Posted by adhsquirrel

Please don't use the word trigate. Its finfet. Trigate existed long before intel used it as a misnomer for marketing purposes. There are not 3 gates. Its one gate with 3 fins. If i make a gate with 5 boards its not 5 gates. A trigate actually has separately accessed gates.

June 5, 2017 | 09:32 PM - Posted by StephanS

I still see AMD on May 24th said 7nm in 2018 (7nm tap out in h2 2017) ... and 7nm+ in 2019.

So is this 5nm coming around 2020 at the soonest or it will be done in parallel ? kind of like the 10nm, 12nm, 14nm we are in now

June 5, 2017 | 10:51 PM - Posted by adhsquirrel

Samsung plans to have risk production on 4nm in 2020. 7nm and 8nm parallel next year. 5 and 6 in 2019. These are not dates we can expect products, but rather, are rough projections when they hope partners can start early runs. My guess is products on shelves would be 7 and 8nm q1 2019 with 5 and 6 q2 2020.

June 7, 2017 | 12:46 AM - Posted by Exascale

Its not like it matters that much anyway. Cost per transistor has been going up since after 22nm. Same with dark silicon because of power density.

The real issue, as has become apparent on the race to exascale, is that the rest of the system is the bottleneck.

The interconnect, memory and storage are the problem, not transistors being too big. The node names have also been all but meaningless for a while too.

Moving data around has become the real cost, and thats why everyone building supercomputers, and those who design the chips for them, are focused on things like silicon photonics, nonvolatile memory(XPoint, NRAM, STT-MRAM Re-RAM), HMC or HBM, and newer data locality friendly programming schemes.

We could still have 22nm transistors, and if the syatem used XPoint or NRAM in addition to its DDR4 and a fast NVMe SSD, it would do most things several times faster than a conventional PC.

Graphics does require a lot of FLOPS though, so they still see a real benefit of smaller nodes, where as CPUs havent recently. GPUs also have increased the amount of RAM and memory bandwidth many times over in the same time that CPUs have increased 25% typical performance(from Sandy Bridge to Kaby Lake).

June 8, 2017 | 12:54 PM - Posted by psuedonymous

"We could still have 22nm transistors, and if the syatem used XPoint or NRAM in addition to its DDR4 and a fast NVMe SSD, it would do most things several times faster than a conventional PC. "

If things were that simple, /we would still be seeing chips fabbed on 22nm/. Use all our old cost-amortised production gear to make faster chips? A no-brainer!

We've been power limited for generations. To reduce per-transistor power means you need smaller transistors to reduce switching energy. Smaller transistors require smaller process scales. No chemistry other than doped Silicon has come even close to demonstrating suitability for use in ICs (GaN power amplifiers are another matter entirely), so we're going to be power limited for many years to come.

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