Anandtech Teaches Some Physics

Subject: General Tech | October 13, 2014 - 11:57 PM |
Tagged: processors, microprocessor, FinFET, fab

Ah, Solid State Physics. Semiconductors are heavily based on this branch, because it explains the physical (mechanical, electrical, thermal, etc.) properties of solids based on how their atoms are organized. These properties lead into how transistors function, and why.

View Full Size

Put it back, Allyn.

Anandtech has published a seven-page article that digs into physics and builds upon itself. It starts with a brief explanation of conductivity and what makes up the difference between a conductor, an insulator, and a semiconductor. It uses that to build a simple transistor. From there it explains logic gates, wafers, and lithography. It works up to FinFETs and then keeps going into the future. It is definitely not an article for beginners, but it can be progressed from start to finish given enough effort on the part of the reader.

While this was not mentioned in the article, at least not that I found, you can derive the number of atoms per "feature" by dividing its size by the lattice-distance of the material. For silicon, that is about half of a nanometer at room temperature. For instance, 14nm means that we are manufacturing features that are defined by less than 30 atoms (up to rounding error). The article speculates a bit about what will happen after the era of silicon. This is quite interesting to me, particularly since I did my undergraduate thesis (just an undergrad thesis) on photonic crystals, which route optical light across manufactured defects in an otherwise opaque solid to make an optical integrated circuit. It has the benefit of, with a mixture of red, orange, and maybe green lasers, being able to "go plaid".

If you are interested, be sure to read the article. It is a bit daunting, but much more manageable than most sources. Congratulations to Joshua Ho and anyone else who might have been involved.

Source: Anandtech

Video News


October 14, 2014 | 09:58 AM - Posted by Anonymous (not verified)

Just go down to the local college library and read some old copies of Microprocessor Report, that and a few others like EE times, the old print editions are a great source, as well as anything from the Hot Chips symposium. there are other older professional journals such as the above that discuss in greater detail what the ARS article briefly summarized. The online sources, some behind a pay wall, are not as easily obtained, but the college libraries usually have access through paid accounts, accessed through the library's public/student computers. If you are lucky enough to live near a college with a computer and materials engineering. or Nano-technology research center, then the best reading sources can be obtained. Stick with the professional trade journals and academic sources, as they are peer reviewed, before publishing.

October 20, 2014 | 11:06 AM - Posted by fade2blac

That article definitely took me back to my days as an undergrad in ECE(Electrical and Computer Engineering). Though at the time I think 0.18 micron was the current TSMC node so things like the more extreme effects of vanishingly small feature sizes was more theory than practice and FinFETs were not yet on the radar. Even back then, I remember the writing being on the wall that increased parallelism and low power/greater efficiency were the future. Limits of photo lithography (wavelength and apertures required to obtain smaller and smaller feature sizes), short channel effects, parasitic capacitance, leakage currents, heat densities, and thermally generated minority carriers...I'm surprised the industry has made it as far as it has. It's interesting to see the strategies being used to keep pushing forward.

However, I'm still not sold on the 16nm FinFETs as the best choice beyond 28nm planar. Fabs have been spending a lot of time and money trying to get FinFETs into production since they are all the rage (16/14nm looks good for marketing). Meanwhile we have generations of CPU/GPU products still stuck at 28nm. These FinFET process nodes seem geared toward power efficiency but tend to plateau quickly when pushed for high power/high frequency applications. This is demonstrated by how compared to Sandy Bridge, Ivy Bridge and Haswell actually lose frequency and can only offer better performance through IPC and efficiency gains.

The below articles seem to point to 20nm FDSOI planar as being more practical in terms of cost of production as well as net density. The semiwiki link in particular does well to point out the fuzzy math involved in declaring feature sizes of FinFET vs planar and what it really means in terms of achievable chip density. The one thing that isn't directly addressed is if 20nm FDSOI is actually well suited for high power applications like GPU/CPU chips.

http://www.advancedsubstratenews.com/2014/03/why-migration-to-fd-soi-is-...

https://www.semiwiki.com/forum/content/3884-who-will-lead-10nm.html

October 15, 2014 | 10:14 AM - Posted by MarkT (not verified)

Great read.

Post new comment

The content of this field is kept private and will not be shown publicly.
  • Lines and paragraphs break automatically.
  • Allowed HTML tags: <a> <em> <strong> <cite> <code> <ul> <ol> <li> <dl> <dt> <dd> <blockquote><p><br>
  • Web page addresses and e-mail addresses turn into links automatically.

More information about formatting options

CAPTCHA
This question is for testing whether you are a human visitor and to prevent automated spam submissions.