Podcast #440 - Ryzen 1 week later, Naples, Logitech G533/G Pro, Riotoro PSU

Subject: Editorial | March 9, 2017 - 12:45 PM |
Tagged: podcast, steamvr, ryzen, riotoro, Oculus, Naples, Loitech, G533, G Pro, arm

PC Perspective Podcast #440 - 03/09/17

Join us for Ryzen 1 week later, Naples, Logitech G533, G Pro, and more!

You can subscribe to us through iTunes and you can still access it directly through the RSS page HERE.

The URL for the podcast is: http://pcper.com/podcast - Share with your friends!

Hosts: Ryan Shrout, Allyn Malventano, Josh Walrath, Jermey Hellstrom

Program length: 1:35:41

 

Source:

March 9, 2017 | 06:40 PM - Posted by Anonymous (not verified)

Seems like Allyn dont give a F unless it's storage :)

March 9, 2017 | 06:54 PM - Posted by Anonymous (not verified)

Yeah, he looks tense and agitated.

March 9, 2017 | 06:59 PM - Posted by Anonymous (not verified)

Storage is Allen's wife and Allen's life!

It's his habit that also pays the bills!

So he get paid and gets benchmarking thrills!

March 9, 2017 | 07:02 PM - Posted by Anonymous (not verified)

edit: Allen
to: Allyn

because I on something, right now!

March 9, 2017 | 06:43 PM - Posted by Anonymous (not verified)

Considering all of the Windows running on ARM server news working it's way around the interwebs currently! Isn't it about time to maybe focus more on asking AMD the status of that other JIM Keller managed/lead CPU project that was going on at the sames time as the Zen development project. AMD's K12 and its first custom designed ARMv8A ISA running micro-architecture that was rumored to be designed very similar to AMD's Zen micro-architecture(Cache, execution units, FP/INT/Branch/etc and SMT) but instead be engineered to run the ARMv8A ISA.

I mean if you watched some of the Jim Keller interviews on YouTube where Keller stated that both the Zen and K12 design teams where sharing some of the very same CPU core design ideas. So will there be a custom K12 ARMv8A ISA running micro-architecture from AMD with SMT abilities and an inner workings that shares some of Zen’s DNA for Cache, Int, FP, Branch prediction, etc!

Zen is out in the wild now! So all but the exact Infinity fabric IP details are known about the Zen/Ryzen and soon to be released Zen/Naples SKUs. And It appears that the ARM market is becoming more important lately with M$ showing off some Windows on ARM related kit along side some x86/open hardware based kit for the server market. There really needs to be some follow up information on AMD’s K12 project from AMD under pressure from so many journalistic sources maybe asking more K12 related questions.

Looking at some of the Zen/Ryzen and Zen/Naples performance metrics one could easily see that the revenues will be there to allow AMD to get a very competitive custom ARMv8A ISA running micro-architecture based series of SKUs out there also and not let any of Keller’s/K12 Design Team’s work go to waste.

AMD, you are not going to do with K12 that very same HP wasteful sort of thing that HP did in canceling that latest ALPHA design back in the days after HP acquired Compaq who earlier had acquired DEC. You Know that ALPHA design that was the first CPU/microprocessor designed to use SMT, only that ALPHA never made it to market because HP was all in with that market failure Itanium protect between itself and Intel!

March 9, 2017 | 11:58 PM - Posted by Anonymous (not verified)

There are plenty of infinity fabric lanes in Zen/Naples "Zepplian" server platform but maybe AMD did not enable enough of the lanes of Infinity fabric for the Zen/Ryzen consumer SKU variants for Inter-CCX unit cache coherency usage/other usage. There is also mentioned some from of Direct Attatched GPU accelorator usage via some infinity fabric IP on Zen/Naples for NVLink style GPU communucation on the Zen/Naples "Zepplian" platform only via some extra MCM extra die IP(I think that was discussed by a Tom's hardware article on Zen/Naples "Zepplian" only).

Anandtech article describes Zen/Naples:

"The top end Naples processor will have a total of 32 cores, with simultaneous multi-threading (SMT), to give a total of 64 threads. This will be paired with eight channels of DDR4 memory, up to two DIMMs per channel for a total of 16 DIMMs, and altogether a single CPU will support 128 PCIe 3.0 lanes. Naples also qualifies as a system-on-a-chip (SoC), with a measure of internal IO for storage, USB and other things, and thus may be offered without a chipset.

Naples will be offered as either a single processor platform (1P), or a dual processor platform (2P). In dual processor mode, and thus a system with 64 cores and 128 threads, each processor will use 64 of its PCIe lanes as a communication bus between the processors as part of AMD’s Infinity Fabric. The Infinity Fabric uses a custom protocol over these lanes, but bandwidth is designed to be on the order of PCIe. As each core uses 64 PCIe lanes to talk to the other, this allows each of the CPUs to give 64 lanes to the rest of the system, totaling 128 PCIe 3.0 again."(1)

later on in the anandtech article:

"Naples uses four of AMD’s Zeppelin dies (the Ryzen dies) in a single package. With each Zeppelin die coming in at 195.2mm2, if it were a monolithic die, that means a total of 780mm2 of silicon, and around 19.2 billion transistors – which is far bigger than anything Global Foundries has ever produced, let alone tried at 14nm. During our interview with Dr. Su, we postulated that multi-die packages would be the way forward on future process nodes given the difficulty of creating these large imposing dies, and the response from Dr. Su indicated that this was a prominent direction to go in.

Each die provides two memory channels, which brings us up to eight channels in total. However, each die only has 16 PCIe 3.0 lanes (24 if you want to count PCH/NVMe), meaning that some form of mux/demux, PCIe switch, or accelerated interface is being used. This could be extra silicon on package, given AMD’s approach of a single die variant of its Zen design to this point.

Note that we’ve seen multi-die packages before in previous products from both AMD and Intel. Despite both companies playing with multi-die or 2.5D technology (AMD with Fury, Intel with EMIB), we are lead to believe that these CPUs are similar to previous multi-chip designs, however there is Infinity Fabric going through them. At what bandwidth, we do not know at this point. It is also pertinent to note that there is a lot of talk going around about the strength of AMD's Infinity Fabric, as well as how threads are manipulated within a silicon die itself, having two core complexes of four cores each. This is something we are investigating on the consumer side, but will likely be very relevant on the enterprise side as well."(1)

(1)

"AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2"

http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for...

P.S. fat chance on getting AMD to fully talk about its infinity fabric IP until the Zen/Naples SKUs are RTM, and even then maybe not all of it!

March 10, 2017 | 12:12 AM - Posted by Anonymous (not verified)

******************Correction*******************

It's not from the toms hardware article but the the direct-attached GPUs info is from Ars Technica article:

"Naples is a two-socket server chip aimed squarely at Intel's Broadwell-EP-based Xeon E5 V4 range, and the overall theme of AMD's chip is "have more of everything." Naples has 32 cores, capable of 64 simultaneous threads, eight memory channels, supporting up to 2TB RAM and 128 PCIe 3.0 lanes. Intel's comparable offering? Twenty-two cores and 44 threads, four memory channels, and a maximum of only 1.5TB RAM.

The PCIe pins are multiplexed and can be used for things other than PCIe. In two-socket systems, 64 of the PCIe lanes from each processor are lost, as the pins are used for inter-socket communication. That leaves 64 from each socket available for I/O. The inter-socket communication uses AMD's "Infinity Fabric," the (somewhat ill-defined) high-speed cache coherent interconnect that's also used within Zen.

Alternatively, those same pins can be used for direct-attached GPUs (which is to say, not using PCIe). That's comparable to what Nvidia is doing with its NVLink interconnect. Later in the year, AMD is going to ship Radeon Instinct headless GPUs. These will be used for both supercomputing-type workloads as well as accelerated graphics in virtualized desktops. The company is promising that at least four Instinct cards can be used with each Naples processor. The same I/O channels will also support Ethernet and NVMe storage; Naples is, like Ryzen, a system-on-a-chip, and it supports up to 12 NVMe drives. It also supports Ethernet, though AMD hasn't specified the number of Ethernet ports supported or the maximum supported link speed."(1)

(1)

"AMD Naples server processor: More cores, bandwidth, memory than Intel"

https://arstechnica.com/information-technology/2017/03/amd-naples-server...

March 10, 2017 | 11:30 AM - Posted by John H (not verified)

Hm, i thought the PS4 Pro / XBone S were on Glofo 14nm first?

March 10, 2017 | 12:42 PM - Posted by Josh Walrath

I think actually TSMC 16nm. Will need to look that up again.

Post new comment

The content of this field is kept private and will not be shown publicly.
  • Lines and paragraphs break automatically.
  • Allowed HTML tags: <a> <em> <strong> <cite> <code> <ul> <ol> <li> <dl> <dt> <dd> <blockquote><p><br>
  • Web page addresses and e-mail addresses turn into links automatically.

More information about formatting options

By submitting this form, you accept the Mollom privacy policy.