Subject: General Tech | October 2, 2018 - 12:00 PM | Ken Addison
Tagged: Xilinx, Versal Prime, Versal AI Core, Versal, FPGA, AI Cores, ACAP
Today at the Xilinx Developer Forum, Xilinx CEO Victor Peng announced a new product family named Versal. Originally revealed earlier in the year as Project Everest, Versal is the first family of devices in what Xilinx is coining as the Adaptive Compute Acceleration Platform (ACAP) market.
ACAPs are a new product segment to solve some of the core difficulties that Xilinx has observed with development via their current FPGA devices. FPGAs traditionally excel in the hands of developers who are more oriented in the hardware world rather than the software world. However, these hardware developers make up only a small percentage compared to the total amount of software developers.
Built from the ground up with complete software programmability in mind, the concept of an ACAP aims to fix this through easy to use software tools, libraries, and runtimes, allowing both the likes of hardware and software developers, as well as data scientists to leverage the power of application acceleration.
In general, ACAPs aim to offer similar performance levels of an ASIC, while still maintaining the highly programmable nature of an FPGA.
Versal, the first device under this ACAP designation, has been developed by Xilinx in a time that they see as the "the era of Heterogeneous compute." Versal tackles this prospect of heterogeneous compute through the use of Scalar Processing Engines, Adaptable Hardware Engines, Intelligent engines, and the integration of advanced interfaces. Versal is built on the cutting edge 7nm FinFET technology from TSMC.