What dwells in the heart of HoloLens? Now we all know!

Subject: General Tech | August 23, 2016 - 12:40 PM |
Tagged: hololens, microsoft, Tensilica, Cherry Trail, hot chips

Microsoft revealed information about the internals of the new holographic processor used in their Hololens at Hot Chips, the first peek we have had.  The new headset is another win for Tensilica as they provide the DSP and instruction extensions; previously we have seen them work with VIA to develop an SSD controller and with AMD for TrueAudio solutions.  Each of the 24 cores has a different task it is hardwired for, offering more efficient processing than software running on flexible hardware.

The processing power for your interface comes from a 14nm Cherry Trail processor with 1GB of DDR and yes, your apps will run on Windows 10.  For now the details are still sparse, there is still a lot to be revealed about Microsoft's answer to VR.  Drop by The Register for more slides and info.


"The secretive HPU is a custom-designed TSMC-fabricated 28nm coprocessor that has 24 Tensilica DSP cores. It has about 65 million logic gates, 8MB of SRAM, and a layer of 1GB of low-power DDR3 RAM on top, all in a 12mm-by-12mm BGA package. We understand it can perform a trillion calculations a second."

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Source: The Register

VIA teams with Tensilica to roll their own SSD controller

Subject: Storage | February 16, 2012 - 09:51 PM |
Tagged: Xtensa, VIA, Tensilica, ssd, DPU, controller

VIA has always been known for the 'slow and steady' approach to computing. They might not have the quickest stuff around, but they certainly tend to have the lowest power draw. While we haven't seen many releases from VIA as of late, they appear to be gearing up for a rediscovered purpose for their mantra - Solid State Storage.

VIA has brought on a company called Tensilica, who make a System on a Chip (SoC) architecture that has been purpose built for moving data around. The system, dubbed the Xtensa dataplane processor (DPU), has some particular math strengths that would be very beneficial if applied to the realm of an SSD controller. For example, the DPU is capable of performing multiple simultaneous table lookups within a single clock cycle. This is handy for increasing the IOPS rating of an SSD, since wear leveling and write amplification are handled by remapping the LBA's (sectors) to flash memory space. Each IO results in a necessary table lookup, which the DPU can perform very quickly.

With the DPU being so efficient at these tasks, it could be run at lower clock speeds and outmaneuver competing SSD controllers - all while consuming less power. We're going to be watching VIA closely in the coming months on this one for sure.
Source: X-bit labs