SK Hynix has huge stacks of NAND

Subject: General Tech | April 11, 2017 - 01:29 PM |
Tagged: SK Hynix, 72 layer, tlc

SK Hynix have created an impressive die which has 72 layers of TLC 3D NAND.  The storage density of their chips are somewhat lower than the competition, this particular chip sports 256Gb of capacity.  This is due to the larger size of SK Hynix's cells, which has the benefit of allowing more layers than other manufacturers have been able to successfully create.  The Register was told that compared to the previous generation of 48 layer NAND you could expect to see up to a 20% increase in read and write speeds, another benefit to their new process.  To think, it was just a year ago that Al first introduced us to what 3D NAND would mean to the PC industry.

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"Korean flash fabber SK Hynix has built a 72-layer 3D NAND die with 256Gb capacity. That number of layers, in effect a higher-rise flash chip than anybody else has built, is impressive but the 256Gb capacity is not; Toshiba's 64-layer flash die has a 512Gb capacity. Like the SK Hynix chip, it is a TLC (3bits/cell) device. It started sample shipping in February."

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Source: The Register

Samsung and SK Hynix Discuss The Future of High Bandwidth Memory (HBM) At Hot Chips 28

Subject: Memory | August 25, 2016 - 02:39 AM |
Tagged: TSV, SK Hynix, Samsung, hot chips, hbm3, hbm

Samsung and SK Hynix were in attendance at the Hot Chips Symposium in Cupertino, California to (among other things) talk about the future of High Bandwidth Memory (HBM). In fact, the companies are working on two new HBM products: HBM3 and an as-yet-unbranded "low cost HBM." HBM3 will replace HBM2 at the high end and is aimed at the HPC and "prosumer" markets while the low cost HBM technology lowers the barrier to entry and is intended to be used in mainstream consumer products.

As currently planned, HBM3 (Samsung refers to its implementation as Extreme HBM) features double the density per layer and at least double the bandwidth of the current HBM2 (which so far is only used in NVIDIA's planned Tesla P100). Specifically, the new memory technology offers up 16Gb (~2GB) per layer and as many as eight (or more) layers can be stacked together using TSVs into a single chip. So far we have seen GPUs use four HBM chips on a single package, and if that holds true with HBM3 and interposer size limits, we may well see future graphics cards with 64GB of memory! Considering the HBM2-based Tesla will have 16 and AMD's HBM-based Fury X cards had 4GB, HBM3 is a sizable jump!

Capacity is not the only benefit though. HBM3 doubles the bandwidth versus HBM2 with 512GB/s (or more) of peak bandwidth per stack! In the theoretical example of a graphics card with 64GB of HBM3 (four stacks), that would be in the range of 2 TB/s of theoretical maximum peak bandwidth! Real world may be less, but still that is many terabytes per second of bandwidth which is exciting because it opens a lot of possibilities for gaming especially as developers push graphics further towards photo realism and resolutions keep increasing. HBM3 should be plenty for awhile as far as keeping the GPU fed with data on the consumer and gaming side of things though I'm sure the HPC market will still crave more bandwidth.

Samsung further claims that HBM3 will operate at similar (~500MHz) clocks to HBM2, but will use "much less" core voltage (HBM2 is 1.2V).

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Stacked HBM memory on an interposer surrounding a processor. Upcoming HBM technologies will allow memory stacks with double the number of layers.

HBM3 is perhaps the most interesting technologically; however, the "low cost HBM" is exciting in that it will enable HBM to be used in the systems and graphics cards most people purchase. There were less details available on this new lower cost variant, but Samsung did share a few specifics. The low cost HBM will offer up to 200GB/s per stack of peak bandwidth while being much cheaper to produce than current HBM2. In order to reduce the cost of production, their is no buffer die or ECC support and the number of Through Silicon Vias (TSV) connections have been reduced. In order to compensate for the lower number of TSVs, the pin speed has been increased to 3Gbps (versus 2Gbps on HBM2). Interestingly, Samsung would like for low cost HBM to support traditional silicon as well as potentially cheaper organic interposers. According to NVIDIA, TSV formation is the most expensive part of interposer fabrication, so making reductions there (and somewhat making up for it in increased per-connection speeds) makes sense when it comes to a cost-conscious product. It is unclear whether organic interposers will win out here, but it is nice to seem them get a mention and is an alternative worth looking into.

Both high bandwidth and low latency memory technologies are still years away and the designs are subject to change, but so far they are both plans are looking rather promising. I am intrigued by the possibilities and hope to see new products take advantage of the increased performance (and in the latter case lower cost). On the graphics front, HBM3 is way too far out to see a Vega release, but it may come just in time for AMD to incorporate it into its high end Navi GPUs, and by 2020 the battle between GDDR and HBM in the mainstream should be heating up.

What are your thoughts on the proposed HBM technologies?

Source: Ars Technica

SK Hynix jumps into Enterprise SSDs with the SE3010

Subject: Storage | June 16, 2016 - 02:54 PM |
Tagged: SK Hynix, enterprise ssd, SE3010

SK Hynix's SE3010 uses their own controller, the eight channel SH87910AA Pearl and in the case of the 960GB model, eight 16nm 128Gb MLC NAND chips with a mysterious H27Q18YEB9a label and four capacitors to prevent data loss in the case of unexpected power loss.  The drive is optimized for read speeds and Kitguru's testing certainly shows that they were effective in their implementation.  Check out the write speed and overall conclusions in the full review.

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"When we last looked at an SSD from SK hynix it was from their consumer portfolio. This time around we are looking at a drive from the other part of their storage business in the shape of the SE3010, a read intensive drive for the Enterprise market space."

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Source: Kitguru

CES 2016: Silicon Motion Updates SM2246EN for 3D NAND, Teases TLC and PCIe

Subject: Storage, Shows and Expos | January 6, 2016 - 06:00 AM |
Tagged: tlc, SM2260, SM2258, SM2256, SM2246EN, slc, SK Hynix, silicon motion, mlc, micron, Intel, imft, CES 2016, CES, 3d nand

Silicon Motion has updated their popular SM2246EN controller to support MLC 3D NAND from IMFT and SK Hynix:

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The SM2246EN acts as a gateway for third parties to make their own SSDs. Adding support for 3D NAND is good news, as it means we will be able to see third party SSDs launch with 3D flash sourced from Intel, Micron, or SK Hynix. Another cool tidbit is the fact that those demo units in the above photo were equipped and operating with actual 3D NAND from Intel, Micron, and SK Hynix. Yes, this is the first time seeing packaged MLC 3D NAND from a company other than Samsung. Here are some close-ups for those who want to read part numbers:

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Another question on non-Samsung 3D NAND is how does its performance stack up against planar (2D) NAND? Silicon Motion had a bit of an answer to that question for us:

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Keep in mind those are results from pre-production firmware, but I was happy to see that my prediction of IMFT 3D NAND speeds being effectively equal to their previous 2D flash was correct.

To knock out some other info overheard at our briefing, Silicon Motion will also be making an SM2258, which will be a TLC 3D NAND variant of the SM2256. In addition, we saw the unreleased SM2260:

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...which is Silicon Motion's PCIe 3.0 x4 SSD controller. This one is expected to surface towards the middle of 2016, and it is currently in the OEM testing stage.

Lots more storage goodies coming later today, so stay tuned! Full press blast for the updates SM2246EN after the break.

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A hint of what to come from Hot Chips

Subject: General Tech | August 25, 2015 - 02:57 PM |
Tagged: amd, hot chips, SK Hynix

Thanks to DigiTimes we are getting some information out of Hot Chips about what is coming up from AMD.  As Sebastian just posted we now have a bit more about the R9 Nano and you can bet we will see more in the near future.  They also describe the new HBM developed in partnership with SK Hynix,  4GB of high-bandwidth memory over a 4096-bit interface will offer an impressive 512Gb/s of memory bandwidth.  We also know a bit more about the new A-series APUs which will range up to 12 compute cores, four Excavator based CPUs and eight GCN based GPUs.  They will also be introducing new power saving features called Adaptive Voltage and Frequency Scaling (AVFS) and will support the new H.265 compression standard.  Click on through to DigiTimes or wait for more pictures and documentation to be released from Hot Chips.

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"AMD is showcasing its new high-performance accelerated processing unit (APU), codenamed Carrizo, and the new AMD Radeon R9 Fury family of GPUs, codenamed Fiji, at the annual Hot Chips symposium."

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Source: DigiTimes