Subject: General Tech | June 7, 2017 - 09:31 PM | Josh Walrath
Tagged: silicon nanosheet, Samsung, IBM, GLOBALFOUNDRIES, FinFET, 5nm
It seems only yesterday that we saw Intel introduce their 22nm FinFET technology, and now we are going all the way down to 5nm. This is obviously an exaggeration. The march of process technology has been more than a little challenging for the past 5+ years for everyone in the industry. Intel has made it look a little easier by being able to finance these advances a little better than the other pure-play foundries. It does not mean that they have not experienced challenges on their own.
We have seen some breakthroughs these past years with everyone jumping onto FinFETs with TSMC, Samsung, and GLOBALFOUNDRIES introducing their own processes. GLOBALFOUNDRIES initially had set out on their own, but that particular endeavor did not pan out. The ended up licensing Samsung’s 14nm processes (LPE and LPP) to start producing chips of their own, primarily for AMD in their graphics and this latest generation of Ryzen CPUs.
These advances have not been easy. While FinFETs are needed at these lower nodes to continue to provide the performance and power efficiency while supporting these transistor densities, the technology will not last forever. 10nm and 7nm lines will continue to use them, but many believe that while we will see the densities improve, the power characteristics will start to lag behind. The theory is that past 7nm nodes traditional FinFETs will no longer work as desired. This is very reminiscent of the sub 28nm processes that attempted to use planar structures on bulk silicon. In that case the chips could be made, but power issues plagued the designs and eventually support for those process lines were dropped.
IBM and their research associates Samsung, GLOBALFOUNDRIES at SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY have announced a breakthrough in a new “Gate-All-Around” architecture made on a 5nm process. FinFETs are essentially a rectangle surround on three sides by gates, giving it the “fin” physical characteristics. This new technology now covers the fourth side and embeds these channels in nanosheets of silicon.
The problem with FinFETs is that they will eventually be unable to scale with power as transistors get closer and closer. While density scales, power and performance will get worse as compared to previous nodes. The 5nm silicon nanosheet technology gives a significant boost to power and efficiency, thereby doing to FinFETs what they did with planar structures at the 20/22nm nodes.
One of the working EUV litho machines at SUNY Albany.
IBM asserts that the average chip the size of a fingernail can contain up to 30 billion transistors and continue to see the density, power, and efficiency improvements that we would expect with a normal process shrink. The company expects these process nodes to start rolling out in a 2019 time frame if all goes as planned.
There are few details in how IBM was able to achieve this result. We do know a couple things about it. EUV lithography was used extensively to avoid the multi-patterning nightmare that this would entail. For the past two years Ametek has been installing 100 watt EUV litho machines throughout the world to select clients. One of these is located on the SUNY Albany campus where this research was done. We also know that deposition was done layer by layer with silicon and the other materials.
What we don’t know is how long it takes to create a complete wafer. Usually these test wafers are packed full of SRAM and very little logic. It is a useful test and creates a baseline for many structures that will eventually be applied to this process. We do not know how long it takes to produce such a wafer, but considering how the layers look to be deposited it takes a long, long time with current tools and machinery. Cutting edge wafers in production can take upwards of 16 weeks to complete. I hesitate to even guess how long each test wafer takes. Because of the very 3D nature of the design, I am curious as to how the litho stages work and how many passes are still needed to complete the design.
This looks to be a very significant advancement in process technology that should be mass produced in the timeline suggested by IBM. It is a significant jump, but it seems to borrow a lot of previous FinFET structures. It does not encompass anything exotic like “quantum wells”, but is able to go lower than the currently specified 7nm processes that TSMC, Samsung, and Intel have hinted at (and yes, process node names should be taken with a grain of salt from all parties at this time). IBM does appear to be comparing this to what Samsung calls its 7nm process in terms of dimensions and transistor density.
Cross section of a 5nm transistor showing the embedded channels and silicon nanosheets.
While Moore’s Law has been stretched thin as of late, we are still seeing these scientists and engineers pushing against the laws of physics to achieve better performance and scaling at incredibly small dimensions. The silicon nanosheet technology looks to be an effective and relatively affordable path towards smaller sizes without requiring exotic materials to achieve. IBM and its partners look to have produced a process node that will continue the march towards smaller, more efficient, and more powerful devices. It is not exactly around the corner, but 2019 is close enough to start planning designs that could potentially utilize this node.
Subject: General Tech | June 5, 2017 - 12:41 PM | Jeremy Hellstrom
Tagged: IBM, global foundries, Samsung, 5nm, 3nm. eulv, GAAFET
Extreme Ultraviolet Lithography has been the hope for reducing process size below the current size but it had not been used to create a successful 5nm chip, until now. IBM, Samsung and GLOBALFOUNDRIES have succeeded in producing a chip using IBM's gate-all-around transistors, which will be known as GAAFETs and will likely replace the current tri-gate FinFETs used today. A GAAFET resembles a FinFET rotated 90 degrees so that the channels run horizontally, stacked three layers high with gates filling in the gaps, hence the name chosen.
Density will go up, this process will fit 30 billion transistors in a 50mm2 chip, 50% more than the previous best commercial process and performance can be increased by 40% at the same power as our current chips or offer the same performance while consuming 75% less power. Ars Technica delves into the technology required to make GAAFETs and more of the potential in their article.
"IBM, working with Samsung and GlobalFoundries, has unveiled the world's first 5nm silicon chip. Beyond the usual power, performance, and density improvement from moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA) transistors, and the first real use of extreme ultraviolet (EUV) lithography."
Here is some more Tech News from around the web:
- Microsoft might be planning a Workstation edition of Windows 10 Pro @ The Inquirer
- Whoops! Microsoft accidentally lets out a mobile-'bricking' OS update @ The Register
- Futuremark PCMark 10 @ techPowerUp
- Google to give 6 months' warning for 2018 Chrome adblockalypse – report @ The Register
- Computex 2017: Gigabyte's latest and greatest gear @ The Tech Report
- The AMD Computex 2017 Press Conference Revealed! @ TechARP
- The Computex Taipei 2017 Live Coverage (Day 4) @ TechARP
Subject: Mobile | May 12, 2017 - 04:33 PM | Jeremy Hellstrom
Tagged: Samsung, DeX, galaxy s8, galaxy s8+
Move over Surface, the new Galaxies are getting a docking station too. The Dex is a charging port with talent, adding USB-A 2.0, ethernet, HDMI, and a USB-C charging port to your phone's capabilities. Plug the dock into a monitor and you will be presented a limited Android system which supports various Samsung apps, as well as Microsoft Office apps, Gmail and YouTube; The Inquirer tested out a few others for compatibility in their review. There is a virtual desktop app that will let you take over a desktop computer as well, according to the page on Samsung. Gaming is not particularly good, unless you utilize the workaround The Inq discovered; pick up a USB C to HDMI adapter and bypass the DeX as opposed to the native screen mirroring which occurs with the DeX software.
"In a nutshell, DeX is a dock for the Galaxy S8 and Galaxy S8+ that outputs a desktop experience from your phone to a big screen. It acts as little more than a portal, relying entirely on your phone's processing power to generate the experience, doing so via HDMI, making it compatible with most TVs and monitors."
Here are some more Mobile articles from around the web:
More Mobile Articles
- The ASUS ZenFone 3 Zoom - iPhone 7 Plus Killer At Half The Price! @ Tech ARP
- LG G6 @ The Inquirer
- The Samsung Galaxy S8 Review - Leaving Apple In The Dust! @ Tech ARP
- The Best Budget Smartphone? A Review Of ZTE’s Blade V8 Pro @ Techgage
Subject: Displays | April 26, 2017 - 06:33 PM | Jeremy Hellstrom
Tagged: Samsung, quantum dots, freesync, CF791
Over the past several years we have discussed the technology behind quantum dots, the new display technology which will provide greatly improved colour representation and gamuts on the next generation of displays. Samsung are one of the first to deliver to market with their CF791 and Kitguru were given the opportunity to review the display. The display is ultrawide, allowing a resolution of 3440x1440 on its 34" screen which has a 1500R curvature. The monitors response time may be unremarkable at 4ms however the refresh rate can reach 100Hz and it is FreeSync compatible. Their testing showed the monitor capable of 100% of sRGB and 84% of AdobeRGB, so this monitor could be effective for either gaming or content creation. Drop by to see the full story.
"Quantum is one of those technology words that seems to generally be associated with good things in computing – like “fuzzy logic” used to be with washing machines. But where the Samsung CF791 is concerned, quantum means something. This is the first screen we have seen with “quantum dot” technology, which is an improvement on regular LCD technology that promises better colour."
Here are some more Display articles from around the web:
- AOC AGON AG251FZ 240Hz FreeSync @ Kitguru
- Acer Predator X34 34-Inch G-Sync Ultrawide 21:9 Gaming Monitor @ eTeknix
- Philips Brilliance 328P 32″ 4K @ Kitguru
- ASUS Designo Curve MX34VQ 34in Curved Monitor @ Kitguru
Subject: Editorial | March 30, 2017 - 10:40 AM | Alex Lustenberg
Tagged: starcraft, Silverstone, Samsung, podcast, Phonoic, Optane, microSD, Lexar, HEX 2.0, drobo, CORSAIR ONE, ashes of the singularity, aida64, 5N2
PC Perspective Podcast #443 - 03/30/17
Join us for Thermoelectric Coolers, Tiny PSUs, Lots o' Storage, some trips down nostaglia lane, and more!
The URL for the podcast is: http://pcper.com/podcast - Share with your friends!
- iTunes - Subscribe to the podcast directly through the iTunes Store (audio only)
- Google Play - Subscribe to our audio podcast directly through Google Play!
- RSS - Subscribe through your regular RSS reader (audio only)
- MP3 - Direct download link to the MP3 file
Hosts: Ryan Shrout, Jeremy Hellstrom, Josh Walrath, Allyn Malventano
Program length: 1:34:48
Today Samsung released an update to their EVO+ microSD card line. The new model is the 'EVO Plus'. Yes, I know, it's confusing to me as well, especially when trying to research the new vs. old iterations for this mini-review. Here's a few quick visual comparisons between both models:
On the left, we have the 'older' version of the Plus (I mean the '+'), while on the right we have the new plus, designated as a '2017 model' on the Samsung site. Note the rating differences between the two. The '+' on the left is rated at UHS-I U1 (10 MB/s minimum write speed), while the newer 'Plus' version is rated at UHS-I U3 (30 MB/s minimum write speed). I also ran across what looked like the older version packaging.
The packaging on the right is what we had in hand for this review. The image on the left was found at the Samsung website, and confuses things even further, as the 'Plus' on the package does not match the markings on the card itself ('+'). It looks as if Samsung may have silently updated the specs of the 256GB '+' model at some point in the recent past, as that model claims significantly faster write speeds (90 MB/s) than the older/other '+' models previously claimed (~20 MB/s). With that confusion out of the way, let's dig into the specs of this newest EVO Plus:
For clarification on the Speed Class and Grade, I direct you to our previous article covering those aspects in detail. For here I'll briefly state that the interface can handle 104 MB/s while the media itself is required to sustain a minimum of 30 MB/s of typical streaming recorded content. The specs go on to claim 100MB/s reads and 90 MB/s writes (60 MB/s for the 64GB model). Doing some quick checks, here's what I saw with some simple file copies to and from a 128GB EVO Plus:
Our figures didn't exceed the specified performance, but they came close, which more than satisfies their 'up to' claim, with over 80 MB/s writes and 93 MB/s reads. I was able to separately confirm 85-89 MB/s writes and 99 MB/s reads with Iometer accessing with 128KB sequential transfers.
- 32GB: $29.99
- 64GB: $49.99
- 128GB: $99.99
- 256GB: coming soon (but there is already a 256GB EVO+ of similar specs???)
Pricing seems to be running a bit high on these, with pricing running close to double of the previous version of this very same part (the EVO+ 128GB can be found for $50 at the time of this writing). Sure you are getting a U3 rated card with over four times the achievable write speed, but the reads are very similar, and if your camera only requires U1 speeds, the price premium does not seem to be worthwhile. It is also worth noting that even faster UHS-II spec cards that transfer at 150 MB/s can be had and even come with a reader at a lower cost.
In summary, the Samsung EVO Plus microSD cards look to be decent performers, but the pricing needs to come down some to be truly competitive in this space. I'd also like to see the product labeling and marketing a bit more clear between the '+' and the 'Plus' models, as they can easily confuse those not so familiar with SD card classes and grades. It also makes searching for them rather difficult, as most search engines parse 'Plus' interchangeably with '+', adding to the potential confusion.
What Makes Ryzen Tick
We have been exposed to details about the Zen architecture for the past several Hot Chips conventions as well as other points of information directly from AMD. Zen was a clean sheet design that borrowed some of the best features from the Bulldozer and Jaguar architectures, as well as integrating many new ideas that had not been executed in AMD processors before. The fusion of ideas from higher performance cores, lower power cores, and experience gained in APU/GPU design have all come together in a very impressive package that is the Ryzen CPU.
It is well known that AMD brought back Jim Keller to head the CPU group after the slow downward spiral that AMD entered in CPU design. While the Athlon 64 was a tremendous part for the time, the subsequent CPUs being offered by the company did not retain that leadership position. The original Phenom had problems right off the bat and could not compete well with Intel’s latest dual and quad cores. The Phenom II shored up their position a bit, but in the end could not keep pace with the products that Intel continued to introduce with their newly minted “tic-toc” cycle. Bulldozer had issues out of the gate and did not have performance numbers that were significantly greater than the previous generation “Thuban” 6 core Phenom II product, much less the latest Intel Sandy Bridge and Ivy Bridge products that it would compete with.
AMD attempted to stop the bleeding by iterating and evolving the Bulldozer architecture with Piledriver, Steamroller, and Excavator. The final products based on this design arc seemed to do fine for the markets they were aimed at, but certainly did not regain any marketshare with AMD’s shrinking desktop numbers. No matter what AMD did, the base architecture just could not overcome some of the basic properties that impeded strong IPC performance.
The primary goal of this new architecture is to increase IPC to a level consistent to what Intel has to offer. AMD aimed to increase IPC per clock by at least 40% over the previous Excavator core. This is a pretty aggressive goal considering where AMD was with the Bulldozer architecture that was focused on good multi-threaded performance and high clock speeds. AMD claims that it has in fact increased IPC by an impressive 54% from the previous Excavator based core. Not only has AMD seemingly hit its performance goals, but it exceeded them. AMD also plans on using the Zen architecture to power products from mobile products to the highest TDP parts offered.
The Zen Core
The basis for Ryzen are the CCX modules. These modules contain four Zen cores along with 8 MB of shared L3 cache. Each core has 64 KB of L1 I-cache and 32 KB of D-cache. There is a total of 512 KB of L2 cache. These caches are inclusive. The L3 cache acts as a victim cache which partially copies what is in L1 and L2 caches. AMD has improved the performance of their caches to a very large degree as compared to previous architectures. The arrangement here allows the individual cores to quickly snoop any changes in the caches of the others for shared workloads. So if a cache line is changed on one core, other cores requiring that data can quickly snoop into the shared L3 and read it. Doing this allows the CPU doing the actual work to not be interrupted by cache read requests from other cores.
Each core can handle two threads, but unlike Bulldozer has a single integer core. Bulldozer modules featured two integer units and a shared FPU/SIMD. Zen gets rid of CMT for good and we have a single integer and FPU units for each core. The core can address two threads by utilizing AMD’s version of SMT (symmetric multi-threading). There is a primary thread that gets higher priority while the second thread has to wait until resources are freed up. This works far better in the real world than in how I explained it as resources are constantly being shuffled about and the primary thread will not monopolize all resources within the core.
Subject: General Tech | February 22, 2017 - 11:27 AM | Jeremy Hellstrom
Tagged: Samsung, note 7
From what Slashdot is reporting we are unlikely to see refurbished Note 7s in North America but they will be appearing in markets on the far side of the Pacific. The battery was determined to be the cause of the rather spectacular failure of Samsung's latest tablet and so they will be installing a battery with a smaller capacity in the refurbished models. One hopes it is physically smaller or more carfeully manufactured, as it was the expansion and puncturing of the battery which caused them to burst into flames. It is understandable that Samsung would like to recoup some losses, this seems like a very risky move to undertake.
"Samsung is said to be swapping the Note 7's 3,500 mAh batteries with a "3,000 to 3,200 mAh" batteries, according to The Korean Economic Daily's sources, predominately for sale in emerging markets such as India and Vietnam."
Here is some more Tech News from around the web:
- AMD's eight-core, 16-thread chips lead the Ryzen charge @ The Tech Report
- Microsoft releases critical Flash patches but leaves zero-day flaws wide open @ The Inquirer
- Remix OS Singularity looks to fight Windows 10 Continuum at its own game @ The Register
- oogle's new mixed reality tech makes VR headsets invisible(ish) @ The Register
- Google rents out Nvidia Tesla GPUs in its cloud. If you ask nicely, that'll be 70 cents an hour, bud @ The Register
- Big Blue's big blunder: IBM accidentally hands over root access to its data science servers @ The Register
- Xiaomi likely to unveil in-house developed CPUs on February 28 @ DigiTimes
Subject: Editorial | February 9, 2017 - 06:59 PM | Josh Walrath
Tagged: TSMC, Samsung, Results, quadro, Q4, nvidia, Intel, geforce, Drive PX2, amd, 2017, 2016
It is most definitely quarterly reports time for our favorite tech firms. NVIDIA’s is unique with their fiscal vs. calendar year as compared to how AMD and Intel report. This has to do when NVIDIA had their first public offering and set the fiscal quarters ahead quite a few months from the actual calendar. So when NVIDIA announces Q4 2017, it is actually reflecting the Q4 period in 2016. Clear as mud?
Semantics aside, NVIDIA had a record quarter. Gross revenue was an impressive $2.173 billion US. This is up slightly more than $700 million from the previous Q4. NVIDIA has shown amazing growth during this time attributed to several factors. Net income (GAAP) is at $655 million. This again is a tremendous amount of profit for a company that came in just over $2 billion in revenue. We can compare this to AMD’s results two weeks ago that hit $1.11 billion in revenue and a loss of $51 million for the quarter. Consider that AMD provides CPUs, chipsets, and GPUs to the market and is the #2 x86 manufacturer in the world.
The yearly results were just as impressive. FY 2017 featured record revenue and net income. Revenue was $6.91 billion as compare to FY 2016 at $5 billion. Net income for the year was $1.666 billion with comparison to $614 million for FY 2016. The growth for the entire year is astounding, and certainly the company had not seen an expansion like this since the early 2000s.
The core strength of the company continues to be gaming. Gaming GPUs and products provided $1.348 billion in revenue by themselves. Since the manufacturing industry was unable to provide a usable 20 nm planar product for large, complex ASICs companies such as NVIDIA and AMD were forced to innovate in design to create new products with greater feature sets and performance, all the while still using the same 28 nm process as previous products. Typically process shrinks accounted for the majority of improvements (more transistors packed into a smaller area with corresponding switching speed increases). Many users kept cards that were several years old due to there not being a huge impetus to upgrade. With the arrival of the 14 nm and 16 nm processes from Samsung and TSMC respectively, users suddenly had a very significant reason to upgrade. NVIDIA was able to address the entire market from high to low with their latest GTX 10x0 series of products. AMD on the other hand only had new products that hit the midrange and budget markets.
The next biggest area for NVIDIA is that of the datacenter. This has seen tremendous growth as compared to the other markets (except of course gaming) that NVIDIA covers. It has gone from around $97 million in Q4 2016 up to $296 million this last quarter. Tripling revenue in any one area is rare. Gaming “only” about doubled during this same time period. Deep learning and AI are two areas that required this type of compute power and NVIDIA was able to deliver a comprehensive software stack, as well as strategic partnerships that provided turnkey solutions for end users.
After datacenter we still have the visualization market based on the Quadro products. This area has not seen the dramatic growth as other aspects of the company, but it remains a solid foundation and a good money maker for the firm. The Quadro products continue to be improved upon and software support grows.
One area that promises to really explode in the next three to four years is the automotive sector. The Drive PX2 system is being integrated into a variety of cars and NVIDIA is focused on providing a solid and feature packed solution for manufacturers. Auto-pilot and “co-pilot” modes will become more and more important in upcoming models and should reach wide availability by 2020, if not a little sooner. NVIDIA is working with some of the biggest names in the industry from both automakers and parts suppliers. BMW should release a fully automated driving system later this year with their i8 series. Audi also has higher end cars in the works that will utilize NVIDIA hardware and fully automated operation. If NVIDIA continues to expand here, eventually it could become as significant a source of income as gaming is today.
There was one bit of bad news from the company. Their OEM & IP division has seen several drops over the past several quarters. NVIDIA announced that the IP licensing to Intel would be discontinued this quarter and would not be renewed. We know that AMD has entered into an agreement with Intel to provide graphics IP to the company in future parts and to cover Intel in potential licensing litigation. This was a fair amount of money per quarter for NVIDIA, but their other divisions more than made up for the loss of this particular income.
NVIDIA certainly seems to be hitting on all cylinders and is growing into markets that previously were unavailable as of five to ten years ago. They are spreading out their financial base so as to avoid boom and bust cycles of any one industry. Next quarter NVIDIA expects revenue to be down seasonally into the $1.9 billion range. Even though that number is down, it would still represent the 3rd highest quarterly revenue.
Subject: Processors | February 8, 2017 - 09:38 PM | Josh Walrath
Tagged: Zen, Skylake, Samsung, ryzen, kaby lake, ISSCC, Intel, GLOBALFOUNDRIES, amd, AM4, 14 nm FinFET
Yesterday EE Times posted some interesting information that they had gleaned at ISSCC. AMD released a paper describing the design process and advances they were able to achieve with the Zen architecture manufactured on Samsung’s/GF’s 14nm FinFETT process. AMD went over some of the basic measurements at the transistor scale and how it compares to what Intel currently has on their latest 14nm process.
The first thing that jumps out is that AMD claimes that their 4 core/8 thread x86 core is about 10% smaller than what Intel has with one of their latest CPUs. We assume it is either Kaby Lake or Skylake. AMD did not exactly go over exactly what they were counting when looking at the cores because there are some significant differences between the two architectures. We are not sure if that 44mm sq. figure includes the L3 cache or the L2 caches. My guess is that it probably includes L2 cache but not L3. I could be easily wrong here.
Going down the table we see that AMD and Samsung/GF are able to get their SRAM sizes down smaller than what Intel is able to do. AMD has double the amount of L2 cache per core, but it is only about 60% larger than Intel’s 256 KB L2. AMD also has a much smaller L3 cache as well than Intel. Both are 8 MB units but AMD comes in at 16 mm sq. while Intel is at 19.1 mm sq. There will be differences in how AMD and Intel set up these caches, and until we see L3 performance comparisons we cannot assume too much.
(Image courtesy of ISSCC)
In some of the basic measurements of the different processes we see that Intel has advantages throughout. This is not surprising as Intel has been well known to push process technology beyond what others are able to do. In theory their products will have denser logic throughout, including the SRAM cells. When looking at this information we wonder how AMD has been able to make their cores and caches smaller. Part of that is due to the likely setup of cache control and access.
One of the most likely culprits of this smaller size is that the less advanced FPU/SSE/AVX units that AMD has in Zen. They support AVX-256, but it has to be done in double the cycles. They can do single cycle AVX-128, but Intel’s throughput is much higher than what AMD can achieve. AVX is not the end-all, be-all but it is gaining in importance in high performance computing and editing applications. David Kanter in his article covering the architecture explicitly said that AMD made this decision to lower the die size and power constraints for this product.
Ryzen will undoubtedly be a pretty large chip overall once both modules and 16 MB of L3 cache are put together. My guess would be in the 220 mm sq. range, but again that is only a guess once all is said and done (northbridge, southbridge, PCI-E controllers, etc.). What is perhaps most interesting of it all is that AMD has a part that on the surface is very close to the Broadwell-E based Intel i7 chips. The i7-6900K runs at 3.2 to 3.7 GHz, features 8 cores and 16 threads, and around 20 MB of L2/L3 cache. AMD’s top end looks to run at 3.6 GHz, features the same number of cores and threads, and has 20 MB of L2/L3 cache. The Intel part is rated at 140 watts TDP while the AMD part will have a max of 95 watts TDP.
If Ryzen is truly competitive in this top end space (with a price to undercut Intel, yet not destroy their own margins) then AMD is going to be in a good position for the rest of this year. We will find out exactly what is coming our way next month, but all indications point to Ryzen being competitive in overall performance while being able to undercut Intel in TDPs for comparable cores/threads. We are counting down the days...