Subject: Processors | June 15, 2017 - 04:00 PM | Ryan Shrout
Tagged: xeon scalable, xeon, skylake-x, skylake-sp, skylake-ep, ring, mesh, Intel
Though we are just days away from the release of Intel’s Core i9 family based on Skylake-X, and a bit further away from the Xeon Scalable Processor launch using the same fundamental architecture, Intel is sharing a bit of information on how the insides of this processor tick. Literally. One of the most significant changes to the new processor design comes in the form of a new mesh interconnect architecture that handles the communications between the on-chip logical areas.
Since the days of Nehalem-EX, Intel has utilized a ring-bus architecture for processor design. The ring bus operated in a bi-directional, sequential method that cycled through various stops. At each stop, the control logic would determine if data was to be the collected to deposited with that module. These ring bus stops are located at memory controllers, CPU cores / caches, the PCI Express interface, memory controllers, LLCs, etc. This ring bus was fairly simple and easily expandable by simply adding more stops on the ring bus itself.
However, over several generations, the ring bus has become quite large and unwieldly. Compare the ring bus from Nehalem above, to the one for last year’s Xeon E5 v5 platform.
The spike in core counts and other modules caused a ballooning of the ring that eventually turned into multiple rings, complicating the design. As you increase the stops on the ring bus you also increase the physical latency of the messaging and data transfer, for which Intel compensated by increasing bandwidth and clock speed of this interface. The expense of that is power and efficiency.
For an on-die interconnect to remain relevant, it needs to be flexible in bandwidth scaling, reduce latency, and remain energy efficient. With 28-core Xeon processors imminent, and new IO capabilities coming along with it, the time for the ring bus in this space is over.
Starting with the HEDT and Xeon products released this year, Intel will be using a new on-chip design called a mesh that Intel promises will offer higher bandwidth, lower latency, and improved power efficiency. As the name implies, the mesh architecture is one in which each node relays messages through the network between source and destination. Though I cannot share many of the details on performance characteristics just yet, Intel did share the following diagram.
As Intel indicates in its blog on the mesh announcements, this generic diagram “shows a representation of the mesh architecture where cores, on-chip cache banks, memory controllers, and I/O controllers are organized in rows and columns, with wires and switches connecting them at each intersection to allow for turns. By providing a more direct path than the prior ring architectures and many more pathways to eliminate bottlenecks, the mesh can operate at a lower frequency and voltage and can still deliver very high bandwidth and low latency. This results in improved performance and greater energy efficiency similar to a well-designed highway system that lets traffic flow at the optimal speed without congestion.”
The bi-directional mesh design allows a many-core design to offer lower node to node latency than the ring architecture could provide, and by adjusting the width of the interface, Intel can control bandwidth (and by relation frequency). Intel tells us that this can offer lower average latency without increasing power. Though it wasn’t specifically mentioned in this blog, the assumption is that because nothing is free, this has a slight die size cost to implement the more granular mesh network.
Using a mesh architecture offers a couple of capabilities and also requires a few changes to the cache design. By dividing up the IO interfaces (think multiple PCI Express banks, or memory channels), Intel can provide better average access times to each core by intelligently spacing the location of those modules. Intel will also be breaking up the LLC into different segments which will share a “stop” on the network with a processor core. Rather than the previous design of the ring bus where the entirety of the LLC was accessed through a single stop, the LLC will perform as a divided system. However, Intel assures us that performance variability is not a concern:
Negligible latency differences in accessing different cache banks allows software to treat the distributed cache banks as one large unified last level cache. As a result, application developers do not have to worry about variable latency in accessing different cache banks, nor do they need to optimize or recompile code to get a significant performance boosts out of their applications.
There is a lot to dissect when it comes to this new mesh architecture for Xeon Scalable and Core i9 processors, including its overall effect on the LLC cache performance and how it might affect system memory or PCI Express performance. In theory, the integration of a mesh network-style interface could drastically improve the average latency in all cases and increase maximum memory bandwidth by giving more cores access to the memory bus sooner. But, it is also possible this increases maximum latency in some fringe cases.
Further testing awaits for us to find out!
Subject: General Tech | January 13, 2016 - 12:27 PM | Jeremy Hellstrom
Tagged: ring, iot, security, gainspan
The Ring WiFi enabled video doorbell, with optional smartlock compatibility to let visitors in remotely, would also share your WiFi password to anyone who knew how to ask. Just use a Torx screwdriver to pop the doorbell off, press the setup button on the back and connect to the Ring and you can get the networks SSID and PSK in plain text. Thankfully Ring has pushed out an update to resolve this issue but it is a perfect demonstration of the abysmal security on IoT devices and the lack of any thought about security implications by users or makers of these new devices. The Register also mentions the Fitbit Aria bathroom scale as being vulnerable in the exact same way as it also uses Gainspan wireless, though at least the scale is inside your house, not accessible to anyone wandering by.
"Security researchers have discovered a glaring security hole that exposes the home network password of users of a Wi-Fi-enabled video doorbell. The issue – now resolved – underlines how default configurations of IoT components can introduce easy to exploit security holes."
Here is some more Tech News from around the web:
- Google beefs up VR business in bid to challenge HTC and Oculus @ The Inquirer
- Windows 10 shattered Remote Desktop's security defaults – so get patching @ The Register
- PC market suffers 'biggest decline in history' and Windows 10 is to blame @ The Inquirer
- Microsoft kicks VMware right in its weakest, cloudiest spot @ The Register
- Techgage’s Best Of CES 2016 @ Techgage
Subject: General Tech | May 11, 2015 - 12:52 PM | Jeremy Hellstrom
Tagged: iot, ring, digital home, smart home
Ryan was impressed with Google's Nest Learning Digital Thermometre and recommended it a few years back as a great holiday gift, which is still true to this day. A company called Ring is making inroads into the smart home market with their self titled second generation product. Their original product was Doorbot, which some hated and many liked but which is nowhere near as interesting as the new Ring. It is a 720p camera, with a motion sensor, microphone and speaker all powered by the small current provided by your existing doorbell circuits and a battery backup good for about a year. It connects to your house and the Cloud via WiFi and is capable of not only ringing on your iOS7+ or Android 4.0+ phone but also to send the video so you can interact with whoever is at your front door even when you are away. You may not be able to sign for packages remotely but barring that this can be very handy. Read more at The Register.
"Ring is enjoying that classic moment in a company's lifecycle when word has started getting out and orders are coming in at a rate that requires scaling up to the next level. And for good reason too. By all accounts, Ring the video doorbell is an impressive product, successfully navigating the path between hardware, software, smart phones and cloud services to deliver a genuinely innovative product with a real use-case."
Here is some more Tech News from around the web:
- The TR Podcast bonus video: AMD, Zen, Fiji, and more
- IBM expands Power Server range with Watson tech to lure in new big data blood @ The Inquirer
- Snappy Ubuntu Core makes the Chillhub internet fridge a cool idea @ The Inquirer
- Fixstars to release a 6TB SSD with 15nm chips @ The Inquirer
- Tech ARP 2015 Mega Giveaway : Mi In-Ear Headphones
Subject: General Tech | March 6, 2015 - 03:24 PM | Jeremy Hellstrom
Tagged: novachips, ring, ssd
Novachips is giving out some details of a series of large SSDs they are planning to release in April; 2TB, 4TB and 8TB models will use point-to-point ring connections as opposed to the usual parallel arrangements. The speeds are impressive, 360,000 random read/write 4k IOPS
and sequential reads and writes topping out at 1.8GB/sec as is the expected lifespan of the drives which they rate at 10 full drive writes a day for five years. Unfortunately the one stat which was not provided to The Register was the pricing, with these sizes and the new flash arrangement you can expect they will carry a hefty price tag.
"Fancy an 8TB SSD? Put one in a PC or notebook and you've got yourself a smoking hot system, fast and with a gaping capacity for data."
Here is some more Tech News from around the web: