Subject: Storage | May 21, 2018 - 04:31 PM | Allyn Malventano
Tagged: ssd, QLC, NVMe, nand, Intel, Floating Gate, flash, die, 1Tbit
In tandem with Micron's launch of their new enterprise QLC SSDs, there is a broader technology announcement coming out of Intel today. This release covers the fact that Intel and Micron have jointly developed shippable 64-Layer 3D QLC NAND.
IMFT's 3D NAND announcement came back in early 2015, and Intel/Micron Flash Technologies have been pushing their floating gate technology further and further. Not only do we have the QLC announcement today, but with it came talks of progress on 96-layer development as well. Combining QLC with 96-Layer would yield a single die capacity of 1.5 Tbit (192GB), up from the 1 Tbit (128GB) capacity of the 64-Layer QLC die that is now in production.
This new flash won't be meant for power users, but should be completely usable in a general use client SSD, provided there is a bit of SLC (or 3D XPoint???) cache on the front end. QLC does store 33% more data per the same die space, which should eventually translate to a lower $/GB once development costs have been recouped. Here's hoping for lower cost SSDs in the future!
Subject: Storage | May 21, 2018 - 04:30 PM | Allyn Malventano
Tagged: ssd, sata, QLC, nand, micron, enterprise
For those that study how flash memory stores bits, Quad Level Cell technology is a tricky thing to pull off in production. You are taking a single NAND Flash cell and change its stored electron count in such a way that you can later discriminate between SIXTEEN different states.
...we're talking a countable number (dozens to hundreds) of electrons making the difference between a stored 0101 or 0110 in a given cell. Pulling that off in production-capable parts is no small feat, and doing so for enterprise usage first is definitely a bold move. Enter Micron:
The 5210 ION line is a SATA product meant for enterprise usages where the workload is primarily reading. This comes in handy for things like real-time data analytics and content delivery systems, where data is infrequently written but needs to be readable at latencies faster than what HDD's can provide.
These are 2.5" 7mm SSDs that will be available from 1.92TB to 7.68TB (yes, 2TB is the *smallest* available capacity for these!). The idea is to enable an easy upgrade path for larger data systems that already employ SATA or SAS (SAS systems are typically cross-compatible with SATA). For backplanes that are designed for slimmer 7mm drives, this can make for some extreme densities.
These are currently being sampled to some big data companies and should see more general availability in a few months time. Press blast from Micron appears after the break.
Subject: Storage, Shows and Expos | August 8, 2017 - 05:37 PM | Allyn Malventano
Tagged: z-ssd, vnand, V-NAND, Samsung, QLC, FMS 2017, 64-Layer, 3d, 32TB, 1Tbit
As is typically the case for Flash Memory Summit, the Samsung keynote was chock full of goodies:
Samsung kicked off by stating there are a good 5 years of revisions left in store for their V-NAND line, each with a corresponding increase in speed and capacity.
While V-NAND V4 was 64-layer TLC, V5 is a move to QLC, bringing per die capacity to 1Tbit (128 GB per die).
If you were to stack 32 of these new V5 dies per package, and do so in a large enough 2.5" housing, that brings the maximum capacity of such a device to a whopping 128TB!
Samsung also discussed a V2 of their Z-NAND, moving from SLC to MLC while only adding 2-3 us of latency per request. Z-NAND is basically a quicker version of NAND flash designed to compete with 3D XPoint.
M.2 SSDs started life with the working title of NGFF. Fed up with the limitations of this client-intended form factor for the enterprise, Samsung is pushing a slightly larger NGSFF form factor that supports higher capacities per device. Samsung claimed a PM983 NGSFF SSD will hold 16TB, a 1U chassis full of the same 576TB, and a 2U chassis pushing that figure to 1.15PB.
Last up is 'Key Value'. This approach allows the flash to be accessed more directly by the application layer, enabling more efficient use of the flash and therefore higher overall performance.
There were more points brought up that we will be covering later on, but for now here is the full press release that went out during the keynote: (after the break)
Subject: General Tech | August 3, 2017 - 12:00 PM | Alex Lustenberg
Tagged: podcast, wolfenstein, wdc, Vibe, Vega Nano, Threadripper, ryzen 3, radeon rx vega, QLC, htc, Fanatec, Clubsport lite elite, BiCS3, amd, video
PC Perspective Podcast #461 - 08/03/17
Join us for AMD Ryzen 3, Threadripper, Logitech Powerplay, and more!
The URL for the podcast is: http://pcper.com/podcast - Share with your friends!
- iTunes - Subscribe to the podcast directly through the iTunes Store (audio only)
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Hosts: Ryan Shrout, Jeremy Hellstrom, Josh Walrath, Allyn Malventano
Peanut Gallery: Ken Addison, Alex Lustenberg
Program length: 1:38:20
Week in Review:
News items of interest:
1:00:45 Looks Like Vega Nano is GO!
Hardware/Software Picks of the Week
Subject: Storage | August 2, 2017 - 06:21 PM | Allyn Malventano
Tagged: BiCS3, western digital, wdc, WD, tlc, slc, QLC, nand, mlc, flash, 96GB, 768Gb, 3d
A month ago, WD and Toshiba each put out releases related to their BiCS 3D Flash memory. WD announced 96 layers (BiCS4) as their next capacity node, while Toshiba announced them reliably storing four bits per cell (QLC).
WD recently did their own press release related to QLC, partially mirroring Toshiba's announcement, but this one had some additional details on capacity per die, as well as stating their associated technology name used for these shifts. TLC was referred to as "X3", and "X4" is the name for their QLC tech as applied to BiCS. The WD release stated that X4 tech, applied to BiCS3, yields 768Gbit (96GB) per die vs. 512Gbit (64GB) per die for X3 (TLC). Bear in mind that while the release (and the math) states this is a 50% increase, moving from TLC to QLC with the same number of cells does only yields a 33% increase, meaning X4 BiCS3 dies need to have additional cells (and footprint) to add that extra 17%.
The release ends by hinting at X4 being applied to BiCS4 in the future, which is definitely exciting. Merging the two recently announced technologies would yield a theoretical 96-layer BiCS4 die, using X4 QLC technology, yielding 1152 Gbit (144GB) per die. A 16 die stack of which would come to 2,304 GB (1.5x the previously stated 1.5TB figure). The 2304 figure might appear incorrect but consider that we are multiplying two 'odd' capacities together (768 Gbit (1.5x512Gbit for TLC) and 96 layers (1.5x64 for X3).
Press blast appears after the break.
Subject: Storage | June 28, 2017 - 09:49 PM | Allyn Malventano
Tagged: wdc, WD, toshiba, QLC, nand, BiCS, 96-layer, 3d
A couple of announcements out of Toshiba and Western Digital today. First up is Toshiba announcing QLC (4 bit per cell) flash on their existing BiCS 3 (64-layer) technology. QLC may not be the best for endurance as the voltage tolerances become extremely tight with 16 individual voltage states per cell, but Toshiba has been working on this tech for a while now.
In the above slide from the Toshiba keynote at last year's Flash Memory Summit, we see the use case here is for 'archival grade flash', which would still offer fast reads but is not meant to be written as frequently as MLC or TLC flash. Employing QLC in Toshiba's current BiCS 3 (64-layer) flash would enable 1.5TB of storage in a 16-die stack (within one flash memory chip package).
Next up is BiCS 4, which was announced by Western Digital. We knew BiCS 4 was coming but did not know how many layers it would be. We now know that figure, and it is 96. The initial offerings will be the common 256Gbit (32GB) capacity per die, but stacking 96 cells high means the die will come in considerably smaller, meaning more per wafer, ultimately translating to lower cost per GB in your next SSD.
While these announcements are welcome, their timing and coordinated launch from both companies seems odd. Perhaps it has something to do with this?