IDF 2014: HGST announces 3.2TB NVMe SSDs, shingled 10TB HDDs

Subject: Storage, Shows and Expos | September 9, 2014 - 02:00 PM |
Tagged: ssd, SMR, pcie, NVMe, idf 2014, idf, hgst, hdd, 10TB

It's the first day of IDF, so it's only natural that we see a bunch of non-IDF news start pouring out :). I'll kick them off with a few announcements from HGST. First item up is their new SN100 line of PCIe SSDs:

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These are NVMe capable PCIe SSDs, available from 800GB to 3.2TB capacities and in (PCI-based - not SATA) 2.5" as well as half-height PCIe cards.

Next up is an expansion of their HelioSeal (Helium filled) drive line:

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Through the use of Shingled Magnetic Recording (SMR), HGST can make an even bigger improvement in storage densities. This does not come completely free, as due to the way SMR writes to the disk, it is primarily meant to be a sequential write / random access read storage device. Picture roofing shingles, but for hard drives. The tracks are slightly overlapped as they are written to disk. This increases density greatly, but writting to the middle of a shingled section is not possible without potentially overwriting two shingled tracks simultaneously. Think of it as CD-RW writing, but for hard disks. This tech is primarily geared towards 'cold storage', or data that is not actively being written. Think archival data. The ability to still read that data randomly and on demand makes these drives more appealing than retrieving that same data from tape-based archival methods.

Further details on the above releases is scarce at present, but we will keep you posted on further details as they develop.

Full press blast for the SN100 after the break.

Source: HGST

IDF 2014: Intel and Google Announce Reference Design Program, Guaranteed 2 Week AOSP Updates

Subject: Mobile | September 9, 2014 - 01:00 PM |
Tagged: tablet, reference design program, Intel, idf 2014, idf, google, aosp, Android

During today's keynote of the Intel Developer Forum, Google and Intel jointly announced a new program aimed to ease the burden of Android deployment and speed up the operating system update adoption rates that have often plagued the ecosystem.

In today's Android market, whether we are talking about x86 or ARM-based SoC designs, the process to release a point update to the operating system is quite complicated. ODMs have to build unique operating system images for each build and each individual SKU has to pass Google Media Services (GMS). This can be cumbersome and time consuming, slowing down or preventing operating system updates from ever making it to the consumer.

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With the Intel Reference Design Program, the company will provide it's partners with a single binary that allows them to choose from a pre-qualified set of components or a complete bill of materials specification. Obviously this BOM will include Intel x86 processors like Bay Trail but it should help speed up the development time of new hardware platforms. Even better, OEMs and ODMs won't have to worry about dealing with the process of passing GMS certification leaving the hardware vendor to simply release the hardware to the market.

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But, an even bigger step forward, is Intel's commitment on the software side. Everyone knows how fragmented the Android OS market with just 20% of the hardware on the Play Store running Android KitKat. For devices built on the Reference Design Program, Intel is going to guarantee software updates within 2 weeks of AOSP (Android Open Source Project) updates. And, that update support will be given for two years after the release of the launch of the device.

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This combination of hardware and software support from Intel to its hardware ODMs should help ignite some innovation and sales in the x86 Android market. There aren't any partners to announce support for this Reference Design Program but hopefully we'll hear about some before the end of IDF. It will be very interesting to see what ARM (and its partners) respond with. There are plenty of roadblocks holding back the quick uptake of x86 Android tablets but those companies would be blind to ignore the weight that Intel can shift when the want to.

Intel Developer Forum (IDF) 2014 Keynote Live Blog

Subject: Processors, Shows and Expos | September 9, 2014 - 11:02 AM |
Tagged: idf, idf 2014, Intel, keynote, live blog

Today is the beginning of the 2014 Intel Developer Forum in San Francisco!  Join me at 9am PT for the first of our live blogs of the main Intel keynote where we will learn what direction Intel is taking on many fronts!

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Author:
Subject: Processors
Manufacturer: Intel

Server and Workstation Upgrades

Today, on the eve of the Intel Developer Forum, the company is taking the wraps off its new server and workstation class high performance processors, Xeon E5-2600 v3. Known previously by the code name Haswell-EP, the release marks the entry of the latest microarchitecture from Intel to multi-socket infrastructure. Though we don't have hardware today to offer you in-house benchmarks quite yet, the details Intel shared with me last month in Oregon are simply stunning.

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Starting with the E5-2600 v3 processor overview, there are more changes in this product transition than we saw in the move from Sandy Bridge-EP to Ivy Bridge-EP. First and foremost, the v3 Xeons will be available in core counts as high as 18, with HyperThreading allowing for 36 accessible threads in a single CPU socket. A new socket, LGA2011-v3 or R3, allows the Xeon platforms to run a quad-channel DDR4 memory system, very similar to the upgrade we saw with the Haswell-E Core i7-5960X processor we reviewed just last week.

The move to a Haswell-based microarchitecture also means that the Xeon line of processors is getting AVX 2.0, known also as Haswell New Instructions, allowing for 2x the FLOPS per clock per core. It also introduces some interesting changes to Turbo Mode and power delivery we'll discuss in a bit.

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Maybe the most interesting architectural change to the Haswell-EP design is per core P-states, allowing each of the up to 18 cores running on a single Xeon processor to run at independent voltages and clocks. This is something that the consumer variants of Haswell do not currently support - every cores is tied to the same P-state. It turns out that when you have up to 18 cores on a single die, this ability is crucial to supporting maximum performance on a wide array of compute workloads and to maintain power efficiency. This is also the first processor to allow independent uncore frequency scaling, giving Intel the ability to improve performance with available headroom even if the CPU cores aren't the bottleneck.

Continue reading our overview of the new Intel Xeon E5-2600 v3 Haswell-EP Processors!!