Subject: General Tech | February 23, 2017 - 10:45 AM | Jeremy Hellstrom
Tagged: hbll, cache, l3 cache, Last Level Cache
There is an insidious latency gap lurking in your computer between your DRAM and your CPUs L3 cache. The size of the latency depends on your processor as not all L3 cache are created equally but regardless there are wasted CPU cycles which could be reclaimed. Piecemakers Technology, the Industrial Technology Research Institute of Taiwan and Intel are on the case, with a project to design something to fit in that niche between the CPU and DRAM. Their prototype Last Level Cache is a chip with 17ns latency which would improve the efficiency at which L3 cache could be filled to pass onto the next level in the CPU. The Register likens it to the way Intel has fit XPoint between the speed of SSDs and DRAM. It will be interesting to see how this finds its way onto the market.
"Jim Handy of Objective Analysis writes about this: "Furthermore, there's a much larger latency gap between the processor's internal Level 3 cache and the system DRAM than there is between any adjacent cache levels.""
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