AMD Announces Q1 2018 Results

Subject: Processors | April 25, 2018 - 09:45 PM |
Tagged: Zen+, Vega, TSMC, ryzen, Results, Q1 2018, Polaris, GLOBALFOUNDRIES, financials, amd, 7nm, 12nm

Today AMD announced their latest financial results for Q1 2018. We expected it to be a good quarter with their guidance earlier this year, but I doubt many thought it would be as strong as it turned out to be. AMD posted revenue of $1.65 billion with a net income of $81 million. This is up from the expected $1.57 billion that analysts expected from what is typically a slow quarter. This is up 40% from Q1 2017 and its $1.18 billion and up 23% from Q4 2017.

amd_logo_2.png

There are multiple reasons behind this revenue growth. The compute and graphics segment lead the way with $1.12B of revenue. The entire year of 2017 AMD had released parts seemingly nonstop since March and the introduction of Ryzen. Q1 continued this trend with the release of the first Ryzen APUs with Vega Graphics introducing the 2000 series. AMD also ramped up production of the newly released Zen+ Ryzen chips and started shipping those out to retailers and partners alike. Initial mobile Ryzen parts were also introduced and shipped with SKUs being also shipped to partners who have yet to announce and release products based on these chips. Finally the strength of the Radeon graphics chips in both gaming and blockchain applications allowed them a tremendous amount of sellthrough throughout 2017 and into 2018. AMD estimates that 10% of the quarter was due to blockchain demand.

Enterprise, Embedded, and Semi-Custom had a revenue of $532 million, which is lower than most analysts expected. Semi-Custom in particular has seen a decline over the past few quarters with the release and saturation of the market of the latest console platforms utilizing AMD designed chips. It appears as though much of the contract is front loaded in terms of revenue with royalties tapering off over time as sales decrease. AMD did have some significant wins, namely providing Intel with Vega based GPUs to be integrated with Intel’s Kaby Lake-G based units. These declines were offset by the shipment of EPYC based processors that are slowly ramping and being shipped to partners to be integrated into server platforms later this year. We have seen a handful of wins from companies like Dell EMC, but AMD is still slowly re-entering the market that they were forced to abandon with their previous, outdated Opteron products. AMD expects to reach mid-single digit marketshare during 2019, but for now they are just getting off the ground with this platform.

gaap_results.PNG

The company is not standing still or resting on their laurels after the successful and heralded launch of the latest Ryzen 2000 series chips based on the Zen+ architecture. It is aggressively ramping their mobile chips featuring the Zen/Vega combination and have some 25 product wins being released throughout late spring and summer. Overall partners have some 60 products either shipping or will ship later this year featuring Ryzen based CPUs.

There is some fear that AMD will see its GPU sales throughput be impacted by the recent drop of cryptocurrency value. Several years back with the Bitcoin crash we saw a tremendous amount of secondhand product being sold and GPU revenues for the company tanked. AMD is a bit more optimistic about the upcoming quarter as they expect the current cryptocurrency/blockchain market is much more robust and people will be holding onto these cards to mine other products/workloads rather than drop them on eBay. My thought here is that we will see a rise in cards available on the secondary/used market, but quite a bit might be offset by latent gaming demand that has been held back due the outrageous prices of GPUs over the past year. People that have been waiting for prices to get back to MSRP or below will then buy. This could be further enhanced if memory prices start to drop, providing more affordable DDR4 and flash for SSDs.

The company is also forging ahead with advanced process technology. They have recently received silicon back from TSMC’s 7nm process and it looks to be a Vega based product. The rumor surrounding this is that it will be more of a compute platform initially rather than gaming oriented. Later this year AMD expects to receive new EPYC silicon, but it looks as though this will be from GLOBALFOUNDRIES 7nm process. AMD wants to be flexible in terms of manufacturing, but they have a long history with GLOBALFOUNDRIES when it comes to CPU production. The two companies work closely together to make sure the process and CPU design match up as cleanly as possible to allow products such as Zen to reach market successfully. The GPU arm is obviously more flexible here as they have a history with multiple foundry partners throughout the past two decades.

nongaap_results.PNG

AMD has set an aggressive, but achievable, timetable of product releases that is initially focusing on the CPU side but would logically be transitioning to the GPU side. Zen+ is out on time and has met with acclaim from consumers and reviewers alike. The latest GPU products are comparable in performance to what NVIDIA has to offer, though they are less power efficient for that level of performance. The “pipecleaner” Vega on 7nm will pave the way towards Navi based products that look to be introduced next year. AMD could possibly refresh Vega on 12nm, but so far there has been no concrete information that such a product exists. They may very well continue to rely on current Polaris and Vega products throughout the rest of this year while focusing on Navi efforts to have a more competitive part come 2019.

Q2 2018 looks to be another successful quarter for AMD. The company’s outlook calls for revenue in the $1.725 billion range, plus or minus $50 million. AMD expects continued growth in all Ryzen product lines and greater throughput of EPYC based products as companies test and release products based on that platform. The GPU market could remain flat, but will most likely decline. That decline will be more than covered by the sell-through of the Ryzen line from top to bottom.

AMD improved their margin by an impressive 4%. Going from 32% to 36% showed the strength and higher ASPs of both CPU and GPU products. AMD expects another 1% increase over the next quarter. While these are good numbers for AMD, they do not match the 58%+ for NVIDIA and Intel when it comes to their margins. AMD certainly has a lot of room for improvement, and a richer product stack will allow them to achieve greater ASPs and see a rise in their overall margins. If EPYC becomes more successful, then we could see another significant improvement in margins for the company.

AMD is getting back to where they belong in terms of product placement, competitiveness, and financial performance. The company has seen a huge improvement year on year and hopes to continue that with a rich product stack that addresses multiple areas of computing. AI and machine learning is ramping up in the company in terms of software support as they feel their CPUs and GPUs are already good enough to handle the workloads. As more money comes in, they can afford to diversify and create a wider product base to compete in more markets. So far Lisa Su has been very, very successful in helping pull AMD from the ashes to the competitive situation that they currently find themselves in.

 

Source: AMD

AMD will have Ryzen to their Pinnacle next February

Subject: General Tech | September 28, 2017 - 12:23 PM |
Tagged: 12nm, GLOBALFOUNDRIES, amd, ryzen, Pinnacle 7, Pinnacle 5, Pinnacle 3, Pinnacle, x470, b450

DigiTimes reports today that AMD has informed motherboard makers that their new series of chips, the Pinnacle family, will in launch early 2018.  They will lead with the Pinnacle 7 series, with Pinnacle 5 and 3 series arriving in March.  April will see the low powered models while Enterprise will have to wait for the Pro until May.  The chips will be built on GLOFO's 12nm process and will hopefully build on AMD's current successes with Ryzen.  You will also meet the new 400 series chipset, so far the X470 and B450 have been mentioned.  While this is still officially a rumour, it is a fairly solid one. 

Pinnacle_Mountain_Sunrise.jpg

"AMD has informed its partners that it plans to launch in February 2018 an upgrade version of its Ryzen series processors built using a 12nm low-power (12LP) process at Globalfoundries, according to sources at motherboard makers."

Here is some more Tech News from around the web:

Tech Talk

Source: DigiTimes

Podcast #468 - AMD Raven Ridge rumors, Intel and Global Foundries new fabrication technology!

Subject: General Tech | September 21, 2017 - 12:43 PM |
Tagged: z270, windows 10, WD, video, toshiba, ShadowPlay, ryzen, podcast, nvidia, nuc, msi, max-q, Intel, gs63vr, GLOBALFOUNDRIES, gigabyte, EPYC, ansel, 2500U, 12TB

PC Perspective Podcast #468 - 09/21/17

Join us for discussion on AMD Raven Ridge rumors,  Intel and Global Foundries new fabrication technology!

You can subscribe to us through iTunes and you can still access it directly through the RSS page HERE.

The URL for the podcast is: http://pcper.com/podcast - Share with your friends!

Hosts: Ryan Shrout, Josh Walrath, Sebastion Peak, Allyn Malventano

Peanut Gallery: Ken Addison, Alex Lustenberg

Program length: 1:39:59

Podcast topics of discussion:
  1. Week in Review:
  2. News items of interest:
  3. Hardware/Software Picks of the Week
  4. Closing/outro

Subscribe to the PC Perspective YouTube Channel for more videos, reviews and podcasts!!

Source:

GLOBALFOUNDRIES Technical Conference Releases

Subject: General Tech | September 20, 2017 - 09:44 PM |
Tagged: GLOBALFOUNDRIES, FinFET, FD-SOI, 12nm, 14nm, 14nm+, 22FDX, 28FDX, 12FDX, amd, Vega, ryzen

The day after Intel had its Technology and Manufacturing expo in China, GLOBALFOUNDRIES kicks off their own version of the event and has made a significant number of announcements concerning upcoming and next generation process technologies. GF (GLOBALFOUNDRIES) had been the manufacturing arm of AMD until it was spun off as its own entity in 2009. Since then GF has been open to providing fabless semiconductor firms a viable alternative to TSMC and other foundries. Their current 14nm process is licensed from Samsung, as GF had some significant issues getting their own version of that technology into production. GF looks to be moving past their process hiccups in getting to FinFET technologies as well as offering other more unique process nodes that will serve upcoming mobile technologies very well.
 
GloFoundries_logo.jpg
 
The big announcement today was the existence of the 12LP process. This is a "12 nm" process that looks to be based off of their previous 14nm work. It is a highly optimized variant that offers around 15% better density and 10% better performance than current 14/16nm processes from competing firms. Some time back GF announced that it would be skipping the 10nm node and going directly to 7nm, but it seems that market forces have pushed them to further optimize 14nm and offer another step.  Regular process improvement cadences are important to fabless partners as they lay out their roadmaps for future products.
 
12FP is also on track to be Automotive Grade 2 Certified by Q4 2017, which opens it up to a variety of automotive applications. Self-driving cars are the hot topic these days and it appears as though GF will be working with multiple manufacturers including Tesla. The process also has an RF component that can be utilized for those designs.
 
There had been some questions before this about what GF would do between 14nm and their expected 7nm offering. AMD had previously shown a roadmap with the first generation Zen being offered on 14nm and a rather nebulous sounding 14nm+ process. We now know that 12LP is going to be the process that AMD leverages for Zen and Vega refreshes next year. GF is opening up risk production in 1H 2018 for early adopters. This typically means that tuning is still going on with the process, and wafer agreements tend to not hinge on "per good die". Essentially, just as the wording suggest, the monetary risks of production fall more on the partner rather than the foundry. I would expect the Zen/Vega refreshes to start rolling out mid-Summer 2018 if all goes well with 12LP.
 
GF-FAB.jpg
 
RF is getting a lot of attention these days. In the past I had talked quite a bit about FD-SOI and the slow adoption of that technology. In the 5G world that we are heading to, RF is becoming far more important. Currently GF has their 28FDX and 22FDX processes which utilize FD-SOI (Fully Depleted Silicon On Insulator). 22FDX is a dual purpose node that can handle both low-leakage ASICs as well as RF enabled products (think cell-phone modems). GF has also announced a new RF centric process node called 8SW SOI. This is a 300mm wafer based technology at Fab 10 located in East Fishkill, NY. This was once an IBM fab, but was eventually "given" to GF for a variety of reasons. The East Fishkill campus is also a center for testing and advanced process development.
 
22FDX is not limited to ASIC and RF production. GF is announcing that it is offering eMRAM (embedded magnetoresistive non-volatile memory) support. GF claims that ic an retain data through a 260C solder reflow while retaining data for more than 10 years at 125C. These products were developed through a partnership with Everspin Technologies. 1Gb DDR MRAM chips have been sampled and 256Mb DDR MRAM chips are currently available through Everspin. This technology is not limited to standalone chips and can be integrated into SOC designs utilizing eFlash and SRAM interface options.
 
GLOBALFOUNDRIES has had a rocky start since it was spun off from AMD. Due to aggressive financing from multiple sources it has acquired other pure play foundries and garnered loyal partners like AMD who have kept revenue flowing. If GF can execute on these new technologies they will be on a far more even standing with TSMC and attract new customers. GF has the fab space to handle a lot of wafers, but these above mentioned processes could be some of their first truly breakthrough products that differentiates itself from the competition.

Intel Technology and Manufacturing Day in China

Subject: General Tech | September 19, 2017 - 11:33 PM |
Tagged: Intel, China, cannon lake, coffee lake, 10nm, 14nm+, 14nm++, 22FFL, GLOBALFOUNDRIES, Samsung, 22FDX

Today in China Intel is holding their Technology and Manufacturing Day. Unlike previous "IDF" events this appears to be far more centered on the manufacturing aspects of Intel's latest process nodes. During presentations Intel talked about their latest steps down the process ladder to smaller and smaller geometries all the while improving performance and power efficiency.
 
Mark-Bohr-Intel-Manufacturing.jpg
Mark Bohr presenting at Intel Technology and Manufacturing Day in China. (Image courtesy of Intel Corporation)
 
It really does not seem as though 14nm has been around as long as it has, but the first Intel products based on that node were released in the 2nd half of 2014.  Intel has since done further work on the process. Today the company talked about two other processes as well as products being made on these nodes.
 
The 10nm process has been in development for some time and we will not see products this year. Instead we will see two product cycles based on 14nm+ and 14nm++ parts. Intel did show off a wafer of 10nm Cannon Lake dies. Intel claims that their 10nm process is still around 3 years more advanced than the competition. Other foundry groups have announced and shown off 10nm parts, but overall transistor density and performance does not look to match what Intel has to offer.
 
We have often talked about the marketing names that these nodes have been given, and how often their actual specifications have not really lived up to the reality. Intel is not immune to this, but they are closer to describing these structures than the competition. Even though this gap does exist, competition is improving their products and offering compelling solutions at decent prices so that fabless semi firms can mostly keep up with Intel.
 
Stacy-Smith-Intel-Manufacturing.jpg
Nothing like handling a 10nm Cannon Lake wafer with bare hands! (Image courtesy of Intel Corporation)
 
A new and interesting process is being offered by intel in the form of 22FFL. This is an obviously larger process node, but it is highly optimized for low power operation with far better leakage characteristics than the previous 22nm FF process that Intel used all those years ago. This is aimed at the ultra-mobile devices with speeds above 2 GHz. This seems to be a response to other low power lines like the 22FDX product from GLOBALFOUNDRIES. Intel did not mention potential RF implementations which is something of great interest from those also looking at 22FDX.
 
Perhaps the biggest news that was released today is that of Intel Custom Foundry announcing and agreement with ARM to develop and implement those CPUs on the upcoming 10nm process. This can have a potentially huge impact depending on the amount of 10nm line space that Intel is willing to sell to ARM's partners as well as what timelines they are looking at to deliver products. ARM showed off a 10nm test wafer of Cortex-A75 CPUs. The company claims that they were able to design and implement these cores using industry standard design flows (automated place and route, rather than fully custom) and achieving performance in excess of 3 GHz.
 
ARM-Intel-manufcturing.jpg
Gus Yeung of ARM holding a 10nm Cortex-A75 based CPUs designed by Intel. (Image courtesy of Intel Corporation)
 
Intel continues to move forward and invest a tremendous amount of money in their process technology. They have the ability to continue at this rate far beyond that of other competitors. Typically the company does a lot of the heavy lifting with the tools partners, which then trickles down to the other manufacturers. This has allowed Intel to stay so far ahead of the competition, and with the introduction of 14nm+, 14nm++, and 10nm they will keep much of that lead. Now we must wait and see what kind of clockspeed and power performance we see from these new nodes and how well the competition can react and when.

IBM Announces 5nm Breakthrough with Silicon Nanosheet Technology

Subject: General Tech | June 7, 2017 - 09:31 PM |
Tagged: silicon nanosheet, Samsung, IBM, GLOBALFOUNDRIES, FinFET, 5nm

It seems only yesterday that we saw Intel introduce their 22nm FinFET technology, and now we are going all the way down to 5nm.  This is obviously an exaggeration.  The march of process technology has been more than a little challenging for the past 5+ years for everyone in the industry.  Intel has made it look a little easier by being able to finance these advances a little better than the other pure-play foundries.  It does not mean that they have not experienced challenges on their own.

We have seen some breakthroughs these past years with everyone jumping onto FinFETs with TSMC, Samsung, and GLOBALFOUNDRIES introducing their own processes.  GLOBALFOUNDRIES initially had set out on their own, but that particular endeavor did not pan out.  The ended up licensing Samsung’s 14nm processes (LPE and LPP) to start producing chips of their own, primarily for AMD in their graphics and this latest generation of Ryzen CPUs.

NicolasLoubet-1440x960.jpg

These advances have not been easy.  While FinFETs are needed at these lower nodes to continue to provide the performance and power efficiency while supporting these transistor densities, the technology will not last forever.  10nm and 7nm lines will continue to use them, but many believe that while we will see the densities improve, the power characteristics will start to lag behind.  The theory is that past 7nm nodes traditional FinFETs will no longer work as desired.  This is very reminiscent of the sub 28nm processes that attempted to use planar structures on bulk silicon.  In that case the chips could be made, but power issues plagued the designs and eventually support for those process lines were dropped.

IBM and their research associates Samsung, GLOBALFOUNDRIES at SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY have announced a breakthrough in a new “Gate-All-Around” architecture made on a 5nm process.  FinFETs are essentially a rectangle surround on three sides by gates, giving it the “fin” physical characteristics.  This new technology now covers the fourth side and embeds these channels in nanosheets of silicon.

The problem with FinFETs is that they will eventually be unable to scale with power as transistors get closer and closer.  While density scales, power and performance will get worse as compared to previous nodes.  The 5nm silicon nanosheet technology gives a significant boost to power and efficiency, thereby doing to FinFETs what they did with planar structures at the 20/22nm nodes.

ibm-suny-asml-euv-machine-1440x812.jpg

One of the working EUV litho machines at SUNY Albany.

IBM asserts that the average chip the size of a fingernail can contain up to 30 billion transistors and continue to see the density, power, and efficiency improvements that we would expect with a normal process shrink.  The company expects these process nodes to start rolling out in a 2019 time frame if all goes as planned.

There are few details in how IBM was able to achieve this result.  We do know a couple things about it.  EUV lithography was used extensively to avoid the multi-patterning nightmare that this would entail.  For the past two years Ametek has been installing 100 watt EUV litho machines throughout the world to select clients.  One of these is located on the SUNY Albany campus where this research was done.  We also know that deposition was done layer by layer with silicon and the other materials.

What we don’t know is how long it takes to create a complete wafer.  Usually these test wafers are packed full of SRAM and very little logic.  It is a useful test and creates a baseline for many structures that will eventually be applied to this process.  We do not know how long it takes to produce such a wafer, but considering how the layers look to be deposited it takes a long, long time with current tools and machinery.  Cutting edge wafers in production can take upwards of 16 weeks to complete.  I hesitate to even guess how long each test wafer takes.  Because of the very 3D nature of the design, I am curious as to how the litho stages work and how many passes are still needed to complete the design.

This looks to be a very significant advancement in process technology that should be mass produced in the timeline suggested by IBM.  It is a significant jump, but it seems to borrow a lot of previous FinFET structures.  It does not encompass anything exotic like “quantum wells”, but is able to go lower than the currently specified 7nm processes that TSMC, Samsung, and Intel have hinted at (and yes, process node names should be taken with a grain of salt from all parties at this time).  IBM does appear to be comparing this to what Samsung calls its 7nm process in terms of dimensions and transistor density.

Nanosheet-5nm-for-release-1.jpg

Cross section of a 5nm transistor showing the embedded channels and silicon nanosheets.

While Moore’s Law has been stretched thin as of late, we are still seeing these scientists and engineers pushing against the laws of physics to achieve better performance and scaling at incredibly small dimensions.  The silicon nanosheet technology looks to be an effective and relatively affordable path towards smaller sizes without requiring exotic materials to achieve.  IBM and its partners look to have produced a process node that will continue the march towards smaller, more efficient, and more powerful devices.  It is not exactly around the corner, but 2019 is close enough to start planning designs that could potentially utilize this node.

Source: IBM
Author:
Subject: Processors
Manufacturer: AMD

What Makes Ryzen Tick

We have been exposed to details about the Zen architecture for the past several Hot Chips conventions as well as other points of information directly from AMD.  Zen was a clean sheet design that borrowed some of the best features from the Bulldozer and Jaguar architectures, as well as integrating many new ideas that had not been executed in AMD processors before.  The fusion of ideas from higher performance cores, lower power cores, and experience gained in APU/GPU design have all come together in a very impressive package that is the Ryzen CPU.

zen_01.jpg

It is well known that AMD brought back Jim Keller to head the CPU group after the slow downward spiral that AMD entered in CPU design.  While the Athlon 64 was a tremendous part for the time, the subsequent CPUs being offered by the company did not retain that leadership position.  The original Phenom had problems right off the bat and could not compete well with Intel’s latest dual and quad cores.  The Phenom II shored up their position a bit, but in the end could not keep pace with the products that Intel continued to introduce with their newly minted “tic-toc” cycle.  Bulldozer had issues  out of the gate and did not have performance numbers that were significantly greater than the previous generation “Thuban” 6 core Phenom II product, much less the latest Intel Sandy Bridge and Ivy Bridge products that it would compete with.

AMD attempted to stop the bleeding by iterating and evolving the Bulldozer architecture with Piledriver, Steamroller, and Excavator.  The final products based on this design arc seemed to do fine for the markets they were aimed at, but certainly did not regain any marketshare with AMD’s shrinking desktop numbers.  No matter what AMD did, the base architecture just could not overcome some of the basic properties that impeded strong IPC performance.

52_perc_design_opt.png

The primary goal of this new architecture is to increase IPC to a level consistent to what Intel has to offer.  AMD aimed to increase IPC per clock by at least 40% over the previous Excavator core.  This is a pretty aggressive goal considering where AMD was with the Bulldozer architecture that was focused on good multi-threaded performance and high clock speeds.  AMD claims that it has in fact increased IPC by an impressive 54% from the previous Excavator based core.  Not only has AMD seemingly hit its performance goals, but it exceeded them.  AMD also plans on using the Zen architecture to power products from mobile products to the highest TDP parts offered.

 

The Zen Core

The basis for Ryzen are the CCX modules.  These modules contain four Zen cores along with 8 MB of shared L3 cache.  Each core has 64 KB of L1 I-cache and 32 KB of D-cache.  There is a total of 512 KB of L2 cache.  These caches are inclusive.  The L3 cache acts as a victim cache which partially copies what is in L1 and L2 caches.  AMD has improved the performance of their caches to a very large degree as compared to previous architectures.  The arrangement here allows the individual cores to quickly snoop any changes in the caches of the others for shared workloads.  So if a cache line is changed on one core, other cores requiring that data can quickly snoop into the shared L3 and read it.  Doing this allows the CPU doing the actual work to not be interrupted by cache read requests from other cores.

ccx.png

l2_cache.png

l3_cache.png

Each core can handle two threads, but unlike Bulldozer has a single integer core.  Bulldozer modules featured two integer units and a shared FPU/SIMD.  Zen gets rid of CMT for good and we have a single integer and FPU units for each core.  The core can address two threads by utilizing AMD’s version of SMT (symmetric multi-threading).  There is a primary thread that gets higher priority while the second thread has to wait until resources are freed up.  This works far better in the real world than in how I explained it as resources are constantly being shuffled about and the primary thread will not monopolize all resources within the core.

Click here to read more about AMD's Zen architecture in Ryzen!

Author:
Subject: Editorial
Manufacturer: AMD

Zen vs. 40 Years of CPU Development

Zen is nearly upon us.  AMD is releasing its next generation CPU architecture to the world this week and we saw CPU demonstrations and upcoming AM4 motherboards at CES in early January.  We have been shown tantalizing glimpses of the performance and capabilities of the “Ryzen” products that will presumably fill the desktop markets from $150 to $499.  I have yet to be briefed on the product stack that AMD will be offering, but we know enough to start to think how positioning and placement will be addressed by these new products.

zen_01.jpg

To get a better understanding of how Ryzen will stack up, we should probably take a look back at what AMD has accomplished in the past and how Intel has responded to some of the stronger products.  AMD has been in business for 47 years now and has been a major player in semiconductors for most of that time.  It really has only been since the 90s where AMD started to battle Intel head to head that people have become passionate about the company and their products.

The industry is a complex and ever-shifting one.  AMD and Intel have been two stalwarts over the years.  Even though AMD has had more than a few challenging years over the past decade, it still moves forward and expects to compete at the highest level with its much larger and better funded competitor.  2017 could very well be a breakout year for the company with a return to solid profitability in both CPU and GPU markets.  I am not the only one who thinks this considering that AMD shares that traded around the $2 mark ten months ago are now sitting around $14.

 

AMD Through 1996

AMD became a force in the CPU industry due to IBM’s requirement to have a second source for its PC business.  Intel originally entered into a cross licensing agreement with AMD to allow it to produce x86 chips based on Intel designs.  AMD eventually started to produce their own versions of these parts and became a favorite in the PC clone market.  Eventually Intel tightened down on this agreement and then cancelled it, but through near endless litigation AMD ended up with a x86 license deal with Intel.

AMD produced their own Am286 chip that was the first real break from the second sourcing agreement with Intel.  Intel balked at sharing their 386 design with AMD and eventually forced the company to develop its own clean room version.  The Am386 was released in the early 90s, well after Intel had been producing those chips for years. AMD then developed their own version of the Am486 which then morphed into the Am5x86.  The company made some good inroads with these speedy parts and typically clocked them faster than their Intel counterparts (eg. Am486 40 MHz and 80 MHz vs. the Intel 486 DX33 and DX66).  AMD priced these points lower so users could achieve better performance per dollar using the same chipsets and motherboards.

zen_02.jpg

Intel released their first Pentium chips in 1993.  The initial version was hot and featured the infamous FDIV bug.  AMD made some inroads against these parts by introducing the faster Am486 and Am5x86 parts that would achieve clockspeeds from 133 MHz to 150 MHz at the very top end.  The 150 MHz part was very comparable in overall performance to the Pentium 75 MHz chip and we saw the introduction of the dreaded “P-rating” on processors.

There is no denying that Intel continued their dominance throughout this time by being the gold standard in x86 manufacturing and design.  AMD slowly chipped away at its larger rival and continued to profit off of the lucrative x86 market.  William Sanders III set the bar higher about where he wanted the company to go and he started on a much more aggressive path than many expected the company to take.

Click here to read the rest of the AMD processor editorial!

AMD Details Zen at ISSCC

Subject: Processors | February 8, 2017 - 09:38 PM |
Tagged: Zen, Skylake, Samsung, ryzen, kaby lake, ISSCC, Intel, GLOBALFOUNDRIES, amd, AM4, 14 nm FinFET

Yesterday EE Times posted some interesting information that they had gleaned at ISSCC.  AMD released a paper describing the design process and advances they were able to achieve with the Zen architecture manufactured on Samsung’s/GF’s 14nm FinFETT process.  AMD went over some of the basic measurements at the transistor scale and how it compares to what Intel currently has on their latest 14nm process.

icon.jpg

The first thing that jumps out is that AMD claimes that their 4 core/8 thread x86 core is about 10% smaller than what Intel has with one of their latest CPUs.  We assume it is either Kaby Lake or Skylake.  AMD did not exactly go over exactly what they were counting when looking at the cores because there are some significant differences between the two architectures.  We are not sure if that 44mm sq. figure includes the L3 cache or the L2 caches.  My guess is that it probably includes L2 cache but not L3.  I could be easily wrong here.

Going down the table we see that AMD and Samsung/GF are able to get their SRAM sizes down smaller than what Intel is able to do.  AMD has double the amount of L2 cache per core, but it is only about 60% larger than Intel’s 256 KB L2.  AMD also has a much smaller L3 cache as well than Intel.  Both are 8 MB units but AMD comes in at 16 mm sq. while Intel is at 19.1 mm sq.  There will be differences in how AMD and Intel set up these caches, and until we see L3 performance comparisons we cannot assume too much.

Zen-comparison.png

(Image courtesy of ISSCC)

In some of the basic measurements of the different processes we see that Intel has advantages throughout.  This is not surprising as Intel has been well known to push process technology beyond what others are able to do.  In theory their products will have denser logic throughout, including the SRAM cells.  When looking at this information we wonder how AMD has been able to make their cores and caches smaller.  Part of that is due to the likely setup of cache control and access.

One of the most likely culprits of this smaller size is that the less advanced FPU/SSE/AVX units that AMD has in Zen.  They support AVX-256, but it has to be done in double the cycles.  They can do single cycle AVX-128, but Intel’s throughput is much higher than what AMD can achieve.  AVX is not the end-all, be-all but it is gaining in importance in high performance computing and editing applications.  David Kanter in his article covering the architecture explicitly said that AMD made this decision to lower the die size and power constraints for this product.

Ryzen will undoubtedly be a pretty large chip overall once both modules and 16 MB of L3 cache are put together.  My guess would be in the 220 mm sq. range, but again that is only a guess once all is said and done (northbridge, southbridge, PCI-E controllers, etc.).  What is perhaps most interesting of it all is that AMD has a part that on the surface is very close to the Broadwell-E based Intel i7 chips.  The i7-6900K runs at 3.2 to 3.7 GHz, features 8 cores and 16 threads, and around 20 MB of L2/L3 cache.  AMD’s top end looks to run at 3.6 GHz, features the same number of cores and threads, and has 20 MB of L2/L3 cache.  The Intel part is rated at 140 watts TDP while the AMD part will have a max of 95 watts TDP.

If Ryzen is truly competitive in this top end space (with a price to undercut Intel, yet not destroy their own margins) then AMD is going to be in a good position for the rest of this year.  We will find out exactly what is coming our way next month, but all indications point to Ryzen being competitive in overall performance while being able to undercut Intel in TDPs for comparable cores/threads.  We are counting down the days...

Source: AMD

GlobalFoundries to Continue FD-SOI Tech, Adds 12nm “12FDX” Node To Roadmap

Subject: Processors | September 13, 2016 - 06:51 PM |
Tagged: GLOBALFOUNDRIES, FD-SOI, 12FDX, process technology

In addition to the company’s efforts to get its own next generation FinFET process technology up and running, GlobalFoundries announced that will continue to pursue FD-SOI process technology with the addition of a 12nm FD-SOI (FDX in GlobalFoundries parlance) node to its roadmap with a slated release of 2019 at the earliest.

GlobalFoundries.png

FD-SOI stands for Fully Depleted Silicon On Insulator and is a planar process technology that uses a thin insulator on top of the base silicon which is then covered by a very thin layer of silicon that is used as the transistor channel. The promise of FD-SOI is that it offers the performance of a FinFET node with lower power consumption and cost than other bulk processes. While the substrate is more expensive with FD-SOI, it uses 50% of the lithography layers and companies can take advantage of reportedly easy-to-implement body biasing to design a single chip that can fulfill multiple products and roles. For example, in the case of 22FDX – which should start rolling out towards the end of this year – GlobalFoundries claims that it offers the performance of 14 FinFET at the 28nm bulk pricing. 22FDX is actually a 14nm front end (FEOL) and 28nm back end of line (BEOL) combined. Notably, it purportedly uses 70% lower power than 28nm HKMG.

22FDX Body Biasing.jpg

A GloFo 22nm FD-SOI "22FDX" transistor.

The FD-SOI design offers lower static leakage and allows chip makers to use body biasing (where substrate is polarized) to balance performance and leakage. Forward Body Biasing allows the transistor to switch faster and/or operate at much lower voltages. On the other hand, Reverse Body Biasing further reduces leakage and frequency to improves energy efficiency. Dynamic Body Biasing (video link) allows for things like turbo modes whereby increasing voltage to the back gate can increase transistor switching speed or reducing voltage can reduce switching speeds and leakage. For a process technology that is aimed at battery powered wearables, mobile devices, and various Internet of Things products, energy efficiency and being able to balance performance and power depending on what is needed is important.

Dyanmic Body Biasing.jpg

22FDX offers body biasing.

While the process node numbers are not as interesting as the news that FD-SOI will continue itself (thanks to marketing mucking up things heh), GlobalFoundries did share that 12FDX (12nm FD-SOI) will be a true full node shrink that will offer the performance of 10nm FinFET (presumably its own future FinFET tech though they do not specify) with better power characteristics and lower cost than 16nm FinFET. I am not sure if GlobalFoundries is using theoretical numbers or compared it to TSMC’s process here since they do not have their own 16nm FinFET process. Further, 12FDX will feature 15% higher performance and up to 50% lower power consumption that today’s FinFET technologies. The future process is aimed at the “cost sensitive mobile market” that includes IoT, automotive (entertainment and AI), mobile, and networking. FD-SOI is reportedly well suited for processors that combine both digital and analog (RF) elements as well.

Following the roll out of 22FDX GlobalFoundries will be preparing its Fab 1 facility in Dresden, Germany for the 12nm FD-SOI (12FDX) process. The new process is slated to begin tapping out products in early 2019 which should mean products using chips will hit the market in 2020.

The news is interesting because it indicates that there is still interest and research/development being made on FD-SOI and GlobalFoundries is the first company to talk about next generation process plans. Samsung and STMicroelectronics also support FD-SOI but have not announced their future plans yet.

If I had to guess, Samsung will be the next company to talk about future FD-SOI as the company continues to offer both FinFET and FD-SOI to its customers though they certainly do not talk as much about the latter. What are your thoughts on FD-SOI and its place in the market?

Also read: FD-SOI Expands, But Is It Disruptive? @ EETimes

Source: Tech Report