Subject: General Tech | September 28, 2017 - 12:23 PM | Jeremy Hellstrom
Tagged: 12nm, GLOBALFOUNDRIES, amd, ryzen, Pinnacle 7, Pinnacle 5, Pinnacle 3, Pinnacle, x470, b450
DigiTimes reports today that AMD has informed motherboard makers that their new series of chips, the Pinnacle family, will in launch early 2018. They will lead with the Pinnacle 7 series, with Pinnacle 5 and 3 series arriving in March. April will see the low powered models while Enterprise will have to wait for the Pro until May. The chips will be built on GLOFO's 12nm process and will hopefully build on AMD's current successes with Ryzen. You will also meet the new 400 series chipset, so far the X470 and B450 have been mentioned. While this is still officially a rumour, it is a fairly solid one.
"AMD has informed its partners that it plans to launch in February 2018 an upgrade version of its Ryzen series processors built using a 12nm low-power (12LP) process at Globalfoundries, according to sources at motherboard makers."
Here is some more Tech News from around the web:
- Power meltdown 'fries' SourceForge, knocks site's servers titsup @ The Register
- Intel's self-learning 'Loihi' AI chip wants machines to think like humans @ The Inquirer
- Bell Canada Wants Pirate Websites Blocked For Canadians @ Slashdot
- Have MAC, will hack: iThings have trivial-to-exploit Wi-Fi bug @ The Register
- Samsung tries to catch up Everspin on MRAM @ Electronics Weekly
- Internet Explorer flaw is exposing your search habits @ The Inquirer
- Helium's for balloons and squeaky voices, not this 10TB Toshiba beast @ The Register
Subject: General Tech | September 21, 2017 - 12:43 PM | Alex Lustenberg
Tagged: z270, windows 10, WD, video, toshiba, ShadowPlay, ryzen, podcast, nvidia, nuc, msi, max-q, Intel, gs63vr, GLOBALFOUNDRIES, gigabyte, EPYC, ansel, 2500U, 12TB
PC Perspective Podcast #468 - 09/21/17
Join us for discussion on AMD Raven Ridge rumors, Intel and Global Foundries new fabrication technology!
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Hosts: Ryan Shrout, Josh Walrath, Sebastion Peak, Allyn Malventano
Peanut Gallery: Ken Addison, Alex Lustenberg
Program length: 1:39:59
Week in Review:
News items of interest:
Hardware/Software Picks of the Week
Subject: General Tech | September 20, 2017 - 09:44 PM | Josh Walrath
Tagged: GLOBALFOUNDRIES, FinFET, FD-SOI, 12nm, 14nm, 14nm+, 22FDX, 28FDX, 12FDX, amd, Vega, ryzen
Subject: General Tech | September 19, 2017 - 11:33 PM | Josh Walrath
Tagged: Intel, China, cannon lake, coffee lake, 10nm, 14nm+, 14nm++, 22FFL, GLOBALFOUNDRIES, Samsung, 22FDX
Subject: General Tech | June 7, 2017 - 09:31 PM | Josh Walrath
Tagged: silicon nanosheet, Samsung, IBM, GLOBALFOUNDRIES, FinFET, 5nm
It seems only yesterday that we saw Intel introduce their 22nm FinFET technology, and now we are going all the way down to 5nm. This is obviously an exaggeration. The march of process technology has been more than a little challenging for the past 5+ years for everyone in the industry. Intel has made it look a little easier by being able to finance these advances a little better than the other pure-play foundries. It does not mean that they have not experienced challenges on their own.
We have seen some breakthroughs these past years with everyone jumping onto FinFETs with TSMC, Samsung, and GLOBALFOUNDRIES introducing their own processes. GLOBALFOUNDRIES initially had set out on their own, but that particular endeavor did not pan out. The ended up licensing Samsung’s 14nm processes (LPE and LPP) to start producing chips of their own, primarily for AMD in their graphics and this latest generation of Ryzen CPUs.
These advances have not been easy. While FinFETs are needed at these lower nodes to continue to provide the performance and power efficiency while supporting these transistor densities, the technology will not last forever. 10nm and 7nm lines will continue to use them, but many believe that while we will see the densities improve, the power characteristics will start to lag behind. The theory is that past 7nm nodes traditional FinFETs will no longer work as desired. This is very reminiscent of the sub 28nm processes that attempted to use planar structures on bulk silicon. In that case the chips could be made, but power issues plagued the designs and eventually support for those process lines were dropped.
IBM and their research associates Samsung, GLOBALFOUNDRIES at SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY have announced a breakthrough in a new “Gate-All-Around” architecture made on a 5nm process. FinFETs are essentially a rectangle surround on three sides by gates, giving it the “fin” physical characteristics. This new technology now covers the fourth side and embeds these channels in nanosheets of silicon.
The problem with FinFETs is that they will eventually be unable to scale with power as transistors get closer and closer. While density scales, power and performance will get worse as compared to previous nodes. The 5nm silicon nanosheet technology gives a significant boost to power and efficiency, thereby doing to FinFETs what they did with planar structures at the 20/22nm nodes.
One of the working EUV litho machines at SUNY Albany.
IBM asserts that the average chip the size of a fingernail can contain up to 30 billion transistors and continue to see the density, power, and efficiency improvements that we would expect with a normal process shrink. The company expects these process nodes to start rolling out in a 2019 time frame if all goes as planned.
There are few details in how IBM was able to achieve this result. We do know a couple things about it. EUV lithography was used extensively to avoid the multi-patterning nightmare that this would entail. For the past two years Ametek has been installing 100 watt EUV litho machines throughout the world to select clients. One of these is located on the SUNY Albany campus where this research was done. We also know that deposition was done layer by layer with silicon and the other materials.
What we don’t know is how long it takes to create a complete wafer. Usually these test wafers are packed full of SRAM and very little logic. It is a useful test and creates a baseline for many structures that will eventually be applied to this process. We do not know how long it takes to produce such a wafer, but considering how the layers look to be deposited it takes a long, long time with current tools and machinery. Cutting edge wafers in production can take upwards of 16 weeks to complete. I hesitate to even guess how long each test wafer takes. Because of the very 3D nature of the design, I am curious as to how the litho stages work and how many passes are still needed to complete the design.
This looks to be a very significant advancement in process technology that should be mass produced in the timeline suggested by IBM. It is a significant jump, but it seems to borrow a lot of previous FinFET structures. It does not encompass anything exotic like “quantum wells”, but is able to go lower than the currently specified 7nm processes that TSMC, Samsung, and Intel have hinted at (and yes, process node names should be taken with a grain of salt from all parties at this time). IBM does appear to be comparing this to what Samsung calls its 7nm process in terms of dimensions and transistor density.
Cross section of a 5nm transistor showing the embedded channels and silicon nanosheets.
While Moore’s Law has been stretched thin as of late, we are still seeing these scientists and engineers pushing against the laws of physics to achieve better performance and scaling at incredibly small dimensions. The silicon nanosheet technology looks to be an effective and relatively affordable path towards smaller sizes without requiring exotic materials to achieve. IBM and its partners look to have produced a process node that will continue the march towards smaller, more efficient, and more powerful devices. It is not exactly around the corner, but 2019 is close enough to start planning designs that could potentially utilize this node.
What Makes Ryzen Tick
We have been exposed to details about the Zen architecture for the past several Hot Chips conventions as well as other points of information directly from AMD. Zen was a clean sheet design that borrowed some of the best features from the Bulldozer and Jaguar architectures, as well as integrating many new ideas that had not been executed in AMD processors before. The fusion of ideas from higher performance cores, lower power cores, and experience gained in APU/GPU design have all come together in a very impressive package that is the Ryzen CPU.
It is well known that AMD brought back Jim Keller to head the CPU group after the slow downward spiral that AMD entered in CPU design. While the Athlon 64 was a tremendous part for the time, the subsequent CPUs being offered by the company did not retain that leadership position. The original Phenom had problems right off the bat and could not compete well with Intel’s latest dual and quad cores. The Phenom II shored up their position a bit, but in the end could not keep pace with the products that Intel continued to introduce with their newly minted “tic-toc” cycle. Bulldozer had issues out of the gate and did not have performance numbers that were significantly greater than the previous generation “Thuban” 6 core Phenom II product, much less the latest Intel Sandy Bridge and Ivy Bridge products that it would compete with.
AMD attempted to stop the bleeding by iterating and evolving the Bulldozer architecture with Piledriver, Steamroller, and Excavator. The final products based on this design arc seemed to do fine for the markets they were aimed at, but certainly did not regain any marketshare with AMD’s shrinking desktop numbers. No matter what AMD did, the base architecture just could not overcome some of the basic properties that impeded strong IPC performance.
The primary goal of this new architecture is to increase IPC to a level consistent to what Intel has to offer. AMD aimed to increase IPC per clock by at least 40% over the previous Excavator core. This is a pretty aggressive goal considering where AMD was with the Bulldozer architecture that was focused on good multi-threaded performance and high clock speeds. AMD claims that it has in fact increased IPC by an impressive 54% from the previous Excavator based core. Not only has AMD seemingly hit its performance goals, but it exceeded them. AMD also plans on using the Zen architecture to power products from mobile products to the highest TDP parts offered.
The Zen Core
The basis for Ryzen are the CCX modules. These modules contain four Zen cores along with 8 MB of shared L3 cache. Each core has 64 KB of L1 I-cache and 32 KB of D-cache. There is a total of 512 KB of L2 cache. These caches are inclusive. The L3 cache acts as a victim cache which partially copies what is in L1 and L2 caches. AMD has improved the performance of their caches to a very large degree as compared to previous architectures. The arrangement here allows the individual cores to quickly snoop any changes in the caches of the others for shared workloads. So if a cache line is changed on one core, other cores requiring that data can quickly snoop into the shared L3 and read it. Doing this allows the CPU doing the actual work to not be interrupted by cache read requests from other cores.
Each core can handle two threads, but unlike Bulldozer has a single integer core. Bulldozer modules featured two integer units and a shared FPU/SIMD. Zen gets rid of CMT for good and we have a single integer and FPU units for each core. The core can address two threads by utilizing AMD’s version of SMT (symmetric multi-threading). There is a primary thread that gets higher priority while the second thread has to wait until resources are freed up. This works far better in the real world than in how I explained it as resources are constantly being shuffled about and the primary thread will not monopolize all resources within the core.
Zen vs. 40 Years of CPU Development
Zen is nearly upon us. AMD is releasing its next generation CPU architecture to the world this week and we saw CPU demonstrations and upcoming AM4 motherboards at CES in early January. We have been shown tantalizing glimpses of the performance and capabilities of the “Ryzen” products that will presumably fill the desktop markets from $150 to $499. I have yet to be briefed on the product stack that AMD will be offering, but we know enough to start to think how positioning and placement will be addressed by these new products.
To get a better understanding of how Ryzen will stack up, we should probably take a look back at what AMD has accomplished in the past and how Intel has responded to some of the stronger products. AMD has been in business for 47 years now and has been a major player in semiconductors for most of that time. It really has only been since the 90s where AMD started to battle Intel head to head that people have become passionate about the company and their products.
The industry is a complex and ever-shifting one. AMD and Intel have been two stalwarts over the years. Even though AMD has had more than a few challenging years over the past decade, it still moves forward and expects to compete at the highest level with its much larger and better funded competitor. 2017 could very well be a breakout year for the company with a return to solid profitability in both CPU and GPU markets. I am not the only one who thinks this considering that AMD shares that traded around the $2 mark ten months ago are now sitting around $14.
AMD Through 1996
AMD became a force in the CPU industry due to IBM’s requirement to have a second source for its PC business. Intel originally entered into a cross licensing agreement with AMD to allow it to produce x86 chips based on Intel designs. AMD eventually started to produce their own versions of these parts and became a favorite in the PC clone market. Eventually Intel tightened down on this agreement and then cancelled it, but through near endless litigation AMD ended up with a x86 license deal with Intel.
AMD produced their own Am286 chip that was the first real break from the second sourcing agreement with Intel. Intel balked at sharing their 386 design with AMD and eventually forced the company to develop its own clean room version. The Am386 was released in the early 90s, well after Intel had been producing those chips for years. AMD then developed their own version of the Am486 which then morphed into the Am5x86. The company made some good inroads with these speedy parts and typically clocked them faster than their Intel counterparts (eg. Am486 40 MHz and 80 MHz vs. the Intel 486 DX33 and DX66). AMD priced these points lower so users could achieve better performance per dollar using the same chipsets and motherboards.
Intel released their first Pentium chips in 1993. The initial version was hot and featured the infamous FDIV bug. AMD made some inroads against these parts by introducing the faster Am486 and Am5x86 parts that would achieve clockspeeds from 133 MHz to 150 MHz at the very top end. The 150 MHz part was very comparable in overall performance to the Pentium 75 MHz chip and we saw the introduction of the dreaded “P-rating” on processors.
There is no denying that Intel continued their dominance throughout this time by being the gold standard in x86 manufacturing and design. AMD slowly chipped away at its larger rival and continued to profit off of the lucrative x86 market. William Sanders III set the bar higher about where he wanted the company to go and he started on a much more aggressive path than many expected the company to take.
Subject: Processors | February 8, 2017 - 09:38 PM | Josh Walrath
Tagged: Zen, Skylake, Samsung, ryzen, kaby lake, ISSCC, Intel, GLOBALFOUNDRIES, amd, AM4, 14 nm FinFET
Yesterday EE Times posted some interesting information that they had gleaned at ISSCC. AMD released a paper describing the design process and advances they were able to achieve with the Zen architecture manufactured on Samsung’s/GF’s 14nm FinFETT process. AMD went over some of the basic measurements at the transistor scale and how it compares to what Intel currently has on their latest 14nm process.
The first thing that jumps out is that AMD claimes that their 4 core/8 thread x86 core is about 10% smaller than what Intel has with one of their latest CPUs. We assume it is either Kaby Lake or Skylake. AMD did not exactly go over exactly what they were counting when looking at the cores because there are some significant differences between the two architectures. We are not sure if that 44mm sq. figure includes the L3 cache or the L2 caches. My guess is that it probably includes L2 cache but not L3. I could be easily wrong here.
Going down the table we see that AMD and Samsung/GF are able to get their SRAM sizes down smaller than what Intel is able to do. AMD has double the amount of L2 cache per core, but it is only about 60% larger than Intel’s 256 KB L2. AMD also has a much smaller L3 cache as well than Intel. Both are 8 MB units but AMD comes in at 16 mm sq. while Intel is at 19.1 mm sq. There will be differences in how AMD and Intel set up these caches, and until we see L3 performance comparisons we cannot assume too much.
(Image courtesy of ISSCC)
In some of the basic measurements of the different processes we see that Intel has advantages throughout. This is not surprising as Intel has been well known to push process technology beyond what others are able to do. In theory their products will have denser logic throughout, including the SRAM cells. When looking at this information we wonder how AMD has been able to make their cores and caches smaller. Part of that is due to the likely setup of cache control and access.
One of the most likely culprits of this smaller size is that the less advanced FPU/SSE/AVX units that AMD has in Zen. They support AVX-256, but it has to be done in double the cycles. They can do single cycle AVX-128, but Intel’s throughput is much higher than what AMD can achieve. AVX is not the end-all, be-all but it is gaining in importance in high performance computing and editing applications. David Kanter in his article covering the architecture explicitly said that AMD made this decision to lower the die size and power constraints for this product.
Ryzen will undoubtedly be a pretty large chip overall once both modules and 16 MB of L3 cache are put together. My guess would be in the 220 mm sq. range, but again that is only a guess once all is said and done (northbridge, southbridge, PCI-E controllers, etc.). What is perhaps most interesting of it all is that AMD has a part that on the surface is very close to the Broadwell-E based Intel i7 chips. The i7-6900K runs at 3.2 to 3.7 GHz, features 8 cores and 16 threads, and around 20 MB of L2/L3 cache. AMD’s top end looks to run at 3.6 GHz, features the same number of cores and threads, and has 20 MB of L2/L3 cache. The Intel part is rated at 140 watts TDP while the AMD part will have a max of 95 watts TDP.
If Ryzen is truly competitive in this top end space (with a price to undercut Intel, yet not destroy their own margins) then AMD is going to be in a good position for the rest of this year. We will find out exactly what is coming our way next month, but all indications point to Ryzen being competitive in overall performance while being able to undercut Intel in TDPs for comparable cores/threads. We are counting down the days...
Subject: Processors | September 13, 2016 - 06:51 PM | Tim Verry
Tagged: GLOBALFOUNDRIES, FD-SOI, 12FDX, process technology
In addition to the company’s efforts to get its own next generation FinFET process technology up and running, GlobalFoundries announced that will continue to pursue FD-SOI process technology with the addition of a 12nm FD-SOI (FDX in GlobalFoundries parlance) node to its roadmap with a slated release of 2019 at the earliest.
FD-SOI stands for Fully Depleted Silicon On Insulator and is a planar process technology that uses a thin insulator on top of the base silicon which is then covered by a very thin layer of silicon that is used as the transistor channel. The promise of FD-SOI is that it offers the performance of a FinFET node with lower power consumption and cost than other bulk processes. While the substrate is more expensive with FD-SOI, it uses 50% of the lithography layers and companies can take advantage of reportedly easy-to-implement body biasing to design a single chip that can fulfill multiple products and roles. For example, in the case of 22FDX – which should start rolling out towards the end of this year – GlobalFoundries claims that it offers the performance of 14 FinFET at the 28nm bulk pricing. 22FDX is actually a 14nm front end (FEOL) and 28nm back end of line (BEOL) combined. Notably, it purportedly uses 70% lower power than 28nm HKMG.
A GloFo 22nm FD-SOI "22FDX" transistor.
The FD-SOI design offers lower static leakage and allows chip makers to use body biasing (where substrate is polarized) to balance performance and leakage. Forward Body Biasing allows the transistor to switch faster and/or operate at much lower voltages. On the other hand, Reverse Body Biasing further reduces leakage and frequency to improves energy efficiency. Dynamic Body Biasing (video link) allows for things like turbo modes whereby increasing voltage to the back gate can increase transistor switching speed or reducing voltage can reduce switching speeds and leakage. For a process technology that is aimed at battery powered wearables, mobile devices, and various Internet of Things products, energy efficiency and being able to balance performance and power depending on what is needed is important.
22FDX offers body biasing.
While the process node numbers are not as interesting as the news that FD-SOI will continue itself (thanks to marketing mucking up things heh), GlobalFoundries did share that 12FDX (12nm FD-SOI) will be a true full node shrink that will offer the performance of 10nm FinFET (presumably its own future FinFET tech though they do not specify) with better power characteristics and lower cost than 16nm FinFET. I am not sure if GlobalFoundries is using theoretical numbers or compared it to TSMC’s process here since they do not have their own 16nm FinFET process. Further, 12FDX will feature 15% higher performance and up to 50% lower power consumption that today’s FinFET technologies. The future process is aimed at the “cost sensitive mobile market” that includes IoT, automotive (entertainment and AI), mobile, and networking. FD-SOI is reportedly well suited for processors that combine both digital and analog (RF) elements as well.
Following the roll out of 22FDX GlobalFoundries will be preparing its Fab 1 facility in Dresden, Germany for the 12nm FD-SOI (12FDX) process. The new process is slated to begin tapping out products in early 2019 which should mean products using chips will hit the market in 2020.
The news is interesting because it indicates that there is still interest and research/development being made on FD-SOI and GlobalFoundries is the first company to talk about next generation process plans. Samsung and STMicroelectronics also support FD-SOI but have not announced their future plans yet.
If I had to guess, Samsung will be the next company to talk about future FD-SOI as the company continues to offer both FinFET and FD-SOI to its customers though they certainly do not talk as much about the latter. What are your thoughts on FD-SOI and its place in the market?
Also read: FD-SOI Expands, But Is It Disruptive? @ EETimes
Clean Sheet and New Focus
It is no secret that AMD has been struggling for some time. The company has had success through the years, but it seems that the last decade has been somewhat bleak in terms of competitive advantages. The company has certainly made an impact in throughout the decades with their 486 products, K6, the original Athlon, and the industry changing Athlon 64. Since that time we have had a couple of bright spots with the Phenom II being far more competitive than expected, and the introduction of very solid graphics performance in their APUs.
Sadly for AMD their investment in the “Bulldozer” architecture was misplaced for where the industry was heading. While we certainly see far more software support for multi-threaded CPUs, IPC is still extremely important for most workloads. The original Bulldozer was somewhat rushed to market and was not fully optimized, while the “Piledriver” based Vishera products fixed many of these issues we have not seen the non-APU products updated to the latest Steamroller and Excavator architectures. The non-APU desktop market has been served for the past four years with 32nm PD-SOI based parts that utilize a rebranded chipset base that has not changed since 2010.
Four years ago AMD decided to change course entirely with their desktop and server CPUs. Instead of evolving the “Bulldozer” style architecture featuring CMT (Core Multi-Threading) they were going to do a clean sheet design that focused on efficiency, IPC, and scalability. While Bulldozer certainly could scale the thread count fairly effectively, the overall performance targets and clockspeeds needed to compete with Intel were just not feasible considering the challenges of process technology. AMD brought back Jim Keller to lead this effort, an industry veteran with a huge amount of experience across multiple architectures. Zen was born.
Hot Chips 28
This year’s Hot Chips is the first deep dive that we have received about the features of the Zen architecture. Mike Clark is taking us through all of the changes and advances that we can expect with the upcoming Zen products.
Zen is a clean sheet design that borrows very little from previous architectures. This is not to say that concepts that worked well in previous architectures were not revisited and optimized, but the overall floorplan has changed dramatically from what we have seen in the past. AMD did not stand still with their Bulldozer products, and the latest Excavator core does improve upon the power consumption and performance of the original. This evolution was simply not enough considering market pressures and Intel’s steady improvement of their core architecture year upon year. Zen was designed to significantly improve IPC and AMD claims that this product has a whopping 40% increase in IPC (instructions per clock) from the latest Excavator core.
AMD also has focused on scaling the Zen architecture from low power envelopes up to server level TDPs. The company looks to have pushed down the top end power envelope of Zen from the 125+ watts of Bulldozer/Vishera into the more acceptable 95 to 100 watt range. This also has allowed them to scale Zen down to the 15 to 25 watt TDP levels without sacrificing performance or overall efficiency. Most architectures have sweet spots where they tend to perform best. Vishera for example could scale nicely from 95 to 220 watts, but the design did not translate well into sub-65 watt envelopes. Excavator based “Carrizo” products on the other hand could scale from 15 watts to 65 watts without real problems, but became terribly inefficient above 65 watts with increased clockspeeds. Zen looks to address these differences by being able to scale from sub-25 watt TDPs up to 95 or 100. In theory this should allow AMD to simplify their product stack by offering a common architecture across multiple platforms.