Subject: Processors | September 13, 2016 - 10:51 PM | Tim Verry
Tagged: GLOBALFOUNDRIES, FD-SOI, 12FDX, process technology
In addition to the company’s efforts to get its own next generation FinFET process technology up and running, GlobalFoundries announced that will continue to pursue FD-SOI process technology with the addition of a 12nm FD-SOI (FDX in GlobalFoundries parlance) node to its roadmap with a slated release of 2019 at the earliest.
FD-SOI stands for Fully Depleted Silicon On Insulator and is a planar process technology that uses a thin insulator on top of the base silicon which is then covered by a very thin layer of silicon that is used as the transistor channel. The promise of FD-SOI is that it offers the performance of a FinFET node with lower power consumption and cost than other bulk processes. While the substrate is more expensive with FD-SOI, it uses 50% of the lithography layers and companies can take advantage of reportedly easy-to-implement body biasing to design a single chip that can fulfill multiple products and roles. For example, in the case of 22FDX – which should start rolling out towards the end of this year – GlobalFoundries claims that it offers the performance of 14 FinFET at the 28nm bulk pricing. 22FDX is actually a 14nm front end (FEOL) and 28nm back end of line (BEOL) combined. Notably, it purportedly uses 70% lower power than 28nm HKMG.
A GloFo 22nm FD-SOI "22FDX" transistor.
The FD-SOI design offers lower static leakage and allows chip makers to use body biasing (where substrate is polarized) to balance performance and leakage. Forward Body Biasing allows the transistor to switch faster and/or operate at much lower voltages. On the other hand, Reverse Body Biasing further reduces leakage and frequency to improves energy efficiency. Dynamic Body Biasing (video link) allows for things like turbo modes whereby increasing voltage to the back gate can increase transistor switching speed or reducing voltage can reduce switching speeds and leakage. For a process technology that is aimed at battery powered wearables, mobile devices, and various Internet of Things products, energy efficiency and being able to balance performance and power depending on what is needed is important.
22FDX offers body biasing.
While the process node numbers are not as interesting as the news that FD-SOI will continue itself (thanks to marketing mucking up things heh), GlobalFoundries did share that 12FDX (12nm FD-SOI) will be a true full node shrink that will offer the performance of 10nm FinFET (presumably its own future FinFET tech though they do not specify) with better power characteristics and lower cost than 16nm FinFET. I am not sure if GlobalFoundries is using theoretical numbers or compared it to TSMC’s process here since they do not have their own 16nm FinFET process. Further, 12FDX will feature 15% higher performance and up to 50% lower power consumption that today’s FinFET technologies. The future process is aimed at the “cost sensitive mobile market” that includes IoT, automotive (entertainment and AI), mobile, and networking. FD-SOI is reportedly well suited for processors that combine both digital and analog (RF) elements as well.
Following the roll out of 22FDX GlobalFoundries will be preparing its Fab 1 facility in Dresden, Germany for the 12nm FD-SOI (12FDX) process. The new process is slated to begin tapping out products in early 2019 which should mean products using chips will hit the market in 2020.
The news is interesting because it indicates that there is still interest and research/development being made on FD-SOI and GlobalFoundries is the first company to talk about next generation process plans. Samsung and STMicroelectronics also support FD-SOI but have not announced their future plans yet.
If I had to guess, Samsung will be the next company to talk about future FD-SOI as the company continues to offer both FinFET and FD-SOI to its customers though they certainly do not talk as much about the latter. What are your thoughts on FD-SOI and its place in the market?
Also read: FD-SOI Expands, But Is It Disruptive? @ EETimes
The Really Good Times are Over
We really do not realize how good we had it. Sure, we could apply that to budget surpluses and the time before the rise of global terrorism, but in this case I am talking about the predictable advancement of graphics due to both design expertise and improvements in process technology. Moore’s law has been exceptionally kind to graphics. We can look back and when we plot the course of these graphics companies, they have actually outstripped Moore in terms of transistor density from generation to generation. Most of this is due to better tools and the expertise gained in what is still a fairly new endeavor as compared to CPUs (the first true 3D accelerators were released in the 1993/94 timeframe).
The complexity of a modern 3D chip is truly mind-boggling. To get a good idea of where we came from, we must look back at the first generations of products that we could actually purchase. The original 3Dfx Voodoo Graphics was comprised of a raster chip and a texture chip, each contained approximately 1 million transistors (give or take) and were made on a then available .5 micron process (we shall call it 500 nm from here on out to give a sense of perspective with modern process technology). The chips were clocked between 47 and 50 MHz (though often could be clocked up to 57 MHz by going into the init file and putting in “SET SST_GRXCLK=57”… btw, SST stood for Sellers/Smith/Tarolli, the founders of 3Dfx). This revolutionary graphics card at the time could push out 47 to 50 megapixels and had 4 MB of VRAM and was released in the beginning of 1996.
My first 3D graphics card was the Orchid Righteous 3D. Voodoo Graphics was really the first successful consumer 3D graphics card. Yes, there were others before it, but Voodoo Graphics had the largest impact of them all.
In 1998 3Dfx released the Voodoo 2, and it was a significant jump in complexity from the original. These chips were fabricated on a 350 nm process. There were three chips to each card, one of which was the raster chip and the other two were texture chips. At the top end of the product stack was the 12 MB cards. The raster chip had 4 MB of VRAM available to it while each texture chip had 4 MB of VRAM for texture storage. Not only did this product double performance from the Voodoo Graphics, it was able to run in single card configurations at 800x600 (as compared to the max 640x480 of the Voodoo Graphics). This is the same time as when NVIDIA started to become a very aggressive competitor with the Riva TnT and ATI was about to ship the Rage 128.
Taking a Fresh Look at GLOBALFOUNDRIES
It has been a while since we last talked about GLOBALFOUNDRIES, and it is high time to do so. So why the long wait between updates? Well, I think the long and short of it is a lack of execution from their stated roadmaps from around 2009 on. When GF first came on the scene they had a very aggressive roadmap about where their process technology will be and how it will be implemented. I believe that GF first mentioned a working 28 nm process in a early 2011 timeframe. There was a lot of excitement in some corners as people expected next generation GPUs to be available around then using that process node.
Fab 1 is the facility where all 32 nm SOI and most 28 nm HKMG are produced.
Obviously GF did not get that particular process up and running as expected. In fact, they had some real issues getting 32 nm SOI running in a timely manner. Llano was the first product GF produced on that particular node, as well as plenty of test wafers of Bulldozer parts. Both were delayed from when they were initially expected to hit, and both had fabrication issues. Time and money can fix most things when it comes to process technology, and eventually GF was able to solve what issues they had on their end. 32 nm SOI/HKMG is producing like gangbusters. AMD has improved their designs on their end to make things a bit easier as well at GF.
While shoring up the 32 nm process was of extreme importance to GF, it seemingly took resources away from further developing 28 nm and below processes. While work was still being done on these products, the roadmap was far too aggressive for what they were able to accomplish. The hits just kept coming though. AMD cut back on 32nm orders, which had a financial impact on both companies. It was cheaper for AMD to renegotiate the contract and take a penalty rather than order chips that it simply could not sell. GF then had lots of line space open on 32 nm SOI (Dresden) that could not be filled. AMD then voided another contract in which they suffered a larger penalty by opting to potentially utilize a second source for 28 nm HKMG production of their CPUs and APUs. AMD obviously was very uncomfortable about where GF was with their 28 nm process.
During all of this time GF was working to get their Luther Forest FAB 8 up and running. Building a new FAB is no small task. This is a multi-billion dollar endeavor and any new FAB design will have complications. Happily for GF, the development of this FAB has gone along seemingly according to plan. The FAB has achieved every major milestone in construction and deployment. Still, the risks involved with a FAB that could reach around $8 billion+ are immense.
2012 was not exactly the year that GF expected, or hoped for. It was tough on them and their partners. They also had more expenses such as acquiring Chartered back in 2009 and then acquiring the rather significant stake that AMD had in the company in the first place. During this time ATIC has been pumping money into GF to keep it afloat as well as its aspirations at being a major player in the fabrication industry.
Subject: Editorial | January 17, 2013 - 02:41 AM | Josh Walrath
Tagged: ST Ericsson, planar, PD-SOI, L8580, FinFET, FD-SOI, Cortex A9, cortex a15, arm
SOI has been around for some time now, but in partially depleted form (PD-SOI). Quite a few manufacturers have utilized PD-SOI for their products, such as AMD and IBM (probably the two largest producers of SOI based parts). Oddly enough, Intel has shunned SOI wafers altogether. One would expect Intel to spare no expense to have the fastest semiconductor based chips on the market, but SOI did not provide enough advantages for the chip behemoth to outweigh the nearly 10% increase in wafer and production costs. There were certainly quite a few interesting properties to PD-SOI, but Intel was able to find ways around bulk silicon’s limitations. These non-SOI improvements include stress and strain, low-K dialectrics, high-K metal gates, and now 3D FinFET Technology. Intel simply did not need SOI to achieve the performance they were looking for while still using bulk silicon wafers.
Things started looking a bit grim for SOI as a technology a few years back. AMD was starting to back out of utilizing SOI for sub-32 nm products, and IBM was slowly shifting away from producing chips based on their Power technology. PD-SOI’s days seemed numbered. And they are. That is ok though, as the technology will see a massive uptake with the introduction of Fully Depleted SOI wafers. I will not go into the technology in full right now, but expect another article further into the future. I mentioned in a tweet some days ago that in manufacturing, materials are still king. This looks to hold true with FD-SOI.
Intel had to utilize 3D FinFETs on 22 nm because they simply could not get the performance out of bulk silicon and planar structures. There are advantages and disadvantages to these structures. The advantage is that better power characteristics can be attained without using exotic materials all the while keeping bins high, but the disadvantage is the increased complexity of wafer production with such structures. It is arguable that the increase in complexity completely offsets the price premium of a SOI based solution. We have also seen with the Intel process that while power consumption is decreased as compared to the previous 32 nm process, the switching performance vs. power consumption is certainly not optimal. Hence the reason why we have not seen Intel release Ivy Bridge parts that are clocked significantly faster than last generation Sandy Bridge chips.
FD-SOI and planar structures at 22 nm and 20 nm promise the improve power characteristics as compared to bulk/FinFET. It also looks to improve overall power vs. clockspeed as compared to bulk/FinFET. In a nutshell this means better power consumption as well as a jump in clockspeed as compared to previous generations. Gate first designs using FD-SOI could be very good, but industry analysts say that gate last designs could be “spectacular”.
So what does this have to do with ST Ericsson? They are one of the first companies to show a products based on 28 nm FD-SOI technology. The ARM based NovaThore L8580 is a dual Cortex A9 design with the graphics portion being the IMG SGX544. At first glance we would think that ST is behind the ball, as other manufacturers are releasing Cortex A15 parts which improve IPC by a significant amount. Then we start digging into the details.
The fastest Cortex A9 designs that we have seen so far have been clocked around 1.5 GHz. The L8580 can be clocked up to 2.5 GHz. Whatever IPC improvements we see with A15 are soon washed away by the sheer clockspeed advantage that the L8580 has. While it has been rumored that the Tegra 4 will be clocked up to 2 GHz in tablet form, ST is able to get the L8580 to 2.5 GHz in a smartphone. NVIDIA utilizes a 5th core to improve low power performance, but ST was able to get their chip to run at 0.6v in low power mode. This decrease in complexity combined with what appears to be outstanding electrical and thermal characteristics makes this a very interesting device.
The Cortex A9 cores are not the only ones to see an improvement in clockspeed and power consumption. The well known and extensively used SGX544 graphics portion runs at 600 MHz in a handheld device, and is around 20% faster clocked than other comparable parts.
When we add all these things together we have a product that appears to be head and shoulders above current parts from Qualcomm and Samsung. It also appears that these parts are comparable, if not slightly ahead, of the announced next generation of parts from the Cortex A15 crowd. It stands to reason that ST Ericsson will run away with the market and be included in every new handheld sold from now until the first 22/20 nm parts are released? Unfortunately for ST Ericsson, this is not the case. If there was an Achilles Heel to the L8580 it is that of production capabilities. ST Ericsson started production on FD-SOI wafers this past spring, but it was processing hundreds of wafers a month vs. the thousands that are required for full scale production. We can assume that ST Ericsson has improved this situation, but they are not exactly a powerhouse when it comes to manufacturing prowess. They simply do not seem to have the FD-SOI production capabilities to handle orders from more than a handful of cellphone and table manufacturers.
ST Ericsson has a very interesting part, and it certainly looks to prove the capabilities of FD-SOI when compared to competing products being produced on bulk silicon. The Nova Thor L8580 will gain some new customers with its combination of performance and power characteristics, even though it is using the “older” Cortex A9 design. FD-SOI has certainly caught the industrys’ attention. There are more FD-SOI factoids floating around that I want to cover soon, but these will have to wait. For the time being ST Ericsson is on the cutting edge when it comes to SOI and their proof of concept L8580 seems to have exceeded expectations.