Subject: Editorial, General Tech, Graphics Cards, Processors, Chipsets | June 13, 2014 - 10:45 PM | Scott Michaud
Tagged: x86, restructure, gpu, arm, APU, amd
According to VR-Zone, AMD has reworked their business, last Thursday, sorting each of their projects into two divisions and moving some executives around. The company is now segmented into the "Enterprise, Embedded, and Semi-Custom Business Group", and the "Computing and Graphics Business Group". The company used to be divided between "Computing Solutions", which handled CPUs, APUs, chipsets, and so forth, "Graphics and Visual Solutions", which is best known for GPUs but also contains console royalties, and "All Other", which was... everything else.
Lisa Su, former general manger of global business, has moved up to Chief Operating Officer (COO), along with other changes.
This restructure makes sense for a couple of reasons. First, it pairs some unprofitable ventures with other, highly profitable ones. AMD's graphics division has been steadily adding profitability to the company while its CPU division has been mostly losing money. Secondly, "All Other" is about a nebulous as a name can get. Instead of having three unbalanced divisions, one of which makes no sense to someone glancing at AMD's quarterly earnings reports, they should now have two, roughly equal segments.
At the very least, it should look better to an uninformed investor. Someone who does not know the company might look at the sheet and assume that, if AMD divested from everything except graphics, that the company would be profitable. If, you know, they did not know that console contracts came into their graphics division because their compute division had x86 APUs, and so forth. This setup is now more aligned to customers, not products.
Subject: Processors, Mobile | June 4, 2014 - 03:00 PM | Ryan Shrout
Tagged: computex, computex 2014, arm, cavium, thunderx
While much of the news coming from Computex was centered around PC hardware, many of ARMs partners are making waves as well. Take Cavium for example, introducing the ThunderX CN88XX family of processors. With a completely custom ARMv8 architectural core design, the ThunderX processors will range from 24 to 48 cores and are targeted at large volume servers and cloud infrastructure. 48 cores!
The ThunderX family will be the first SoC to scale up to 48 cores and with a clock speed of 2.5 GHz and 16MB of L2 cache, should offer some truly impressive performance levels. Cavium claims to be the first socket-coherent ARM processor as well, using the Cavium Coherent Processor Interconnect. The I/O capacity stretches into the hundreds of Gigabits and quad channel DDR3 and DDR4 memory speeds up to 2.4 GHz keep the processors fed with work.
Here is the breakdown on the ThunderX families.
ThunderX_CP: Up to 48 highly efficient cores along with integrated virtSOC, dual socket coherency, multiple 10/40 GbE and high memory bandwidth. This family is optimized for private and public cloud web servers, content delivery, web caching, search and social media workloads.
ThunderX_ST: Up to 48 highly efficient cores along with integrated virtSOC, multiple SATAv3 controllers, 10/40 GbE & PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric for east-west as well as north-south traffic connectivity. This family includes hardware accelerators for data protection/ integrity/security, user to user efficient data movement (RoCE) and compressed storage. This family is optimized for Hadoop, block & object storage, distributed file storage and hot/warm/cold storage type workloads.
ThunderX_SC: Up to 48 highly efficient cores along with integrated virtSOC, 10/40 GbE connectivity, multiple PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric for east-west as well as north-south traffic connectivity. The hardware accelerators include Cavium’s industry leading, 4th generation NITROX and TurboDPI technology with acceleration for IPSec, SSL, Anti-virus, Anti-malware, firewall and DPI. This family is optimized for Secure Web front-end, security appliances and Cloud RAN type workloads.
ThunderX_NT: Up to 48 highly efficient cores along with integrated virtSOC, 10/40/100 GbE connectivity, multiple PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric with feature rich capabilities for bandwidth provisioning , QoS, traffic Shaping and tunnel termination. The hardware accelerators include high packet throughput processing, network virtualization and data monitoring. This family is optimized for media servers, scale-out embedded applications and NFV type workloads.
We spoke with ARM earlier this year about its push into the server market and it is partnerships like these that will begin the ramp up to wide spread adoption of ARM-based server infrastructure. The ThunderX family will begin sampling in early Q4 2014 and production should be available by early 2015.
Subject: Processors | May 28, 2014 - 09:09 PM | Sebastian Peak
Tagged: tablet, SoC, Rockchip, mobile, Intel, atom, arm, Android
While details about upcoming Haswell-E processors were reportedly leaking out, an official announcement from Intel was made on Tuesday about another CPU product - and this one isn't a high-end desktop part. The chip giant is partnering with the fabless semiconductor manufacturer Rockchip to create a low-cost SoC for Android devices under the Intel name, reportedly fabricated at TSMC.
We saw almost exactly the opposite of this arrangement last October, when it was announced that Altera would be using Intel to fab ARMv8 chips. Try to digest this: Instead of Intel agreeing to manufacture another company's chip with ARM's architecture in their fabs, they are going through what is said to be China's #1 tablet SoC manufacturer to produce x86 chips...at TSMC? It's a small - no, a strange world we live in!
From Intel's press release: "Under the terms of the agreement, the two companies will deliver an Intel-branded mobile SoC platform. The quad-core platform will be based on an Intel® Atom™ processor core integrated with Intel's 3G modem technology."
As this upcoming x86 SoC is aimed at entry-level Android tablets this announcement might not seem to be exciting news at first glance, but it fills a short term need for Intel in their quest for market penetration in the ultramobile space dominated by ARM-based SoCs. The likes of Qualcomm, Apple, Samsung, TI, and others (including Rockchip's RK series) currently account for 90% of the market, all using ARM.
As previously noted, this partnership is very interesting from an industry standpoint, as Intel is sharing their Atom IP with Rockchip to make this happen. Though if you think back, the move is isn't unprecedented... I recall something about a little company called Advanced Micro Devices that produced x86 chips for Intel in the past, and everything seemed to work out OK there...
When might we expect these new products in the Intel chip lineup codenamed SoFIA? Intel states "the dual-core 3G version (is) expected to ship in the fourth quarter of this year, the quad-core 3G version...expected to ship in the first half of 2015, and the LTE version, also due in the first half of next year." And again, this SoC will only be available in low-cost Android tablets under this partnership (though we might speculate on, say, an x86 SoC powered Surface or Ultrabook in the future?).
Another Boring Presentation...?
In my old age I am turning into a bit of a skeptic. It is hard to really blame a guy; we are surrounded by marketing and hype, both from inside companies and from their fans. When I first started to listen in on AMD’s Core Innovation Update presentation, I was not expecting much. I figured it would be a rehash of the past year, more talk about Mullins/Beema, and some nice words about some of the upcoming Kaveri mobile products.
I was wrong.
AMD decided to give us a pretty interesting look at what they are hoping to accomplish in the next three years. It was not all that long ago that AMD was essentially considered road kill, and there was a lot of pessimism that Rory Read and Co. could turn AMD around. Now after a couple solid years of growth, a laser-like focus on product development based on the IP strengths of the company, and a pretty significant cut of the workforce, we are seeing an AMD that is vastly different from the one that Dirk Meyers was in charge of (or Hector Ruiz for that matter). Their view for the future takes a pretty significant turn from where AMD was even 8 years ago. x86 certainly has a future for AMD, but the full-scale adoption of the ARM architecture looks to be what finally differentiates this company from Intel.
Look, I’m Amphibious!
AMD is not amphibious. They are working on being ambidextrous. Their goal is not only to develop and sell x86 based processors, but also be a prime moving force in the ARM market. AMD has survived against a very large, well funded, and aggressive organization for the past 35 years. They believe their experience here can help them break into, and thrive within, the ARM marketplace. Their goals are not necessarily to be in every smartphone out there, but they are leveraging the ARM architecture to address high growth markets that have a lot of potential.
There are really two dominant architectures in the world with ARM and x86. They power the vast majority of computing devices around the world. Sure, we still have some Power and MIPS implementations, but they are dwarfed by the combined presence of x86 and ARM in modern devices. The flexibility of x86 allows it to scale from the extreme mobile up to the highest performing clusters. ARM also has the ability to scale in performance from handhelds up to the server world, but so far their introduction into servers and HPC solutions has been minimal to non-existent. This is an area that AMD hopes to change, but it will not happen overnight. A lot of infrastructure is needed to get ARM into that particular area. Ask Intel how long it took for x86 to gain a handhold in the lucrative server and workstation markets.
Subject: General Tech | May 8, 2014 - 03:57 PM | Ken Addison
Tagged: podcast, video, asus, z97, Z97-Deluxe, ncase, m1, amd, seattle, arm, nvidia, Portal, shield
PC Perspective Podcast #299 - 05/08/2014
Join us this week as we discuss ASUS Z97-Deluxe, NCASE M1 Case, AMD's custom ARM Designs and more!
The URL for the podcast is: http://pcper.com/podcast - Share with your friends!
- iTunes - Subscribe to the podcast directly through the Store
- RSS - Subscribe through your regular RSS reader
- MP3 - Direct download link to the MP3 file
Hosts: Ryan Shrout, Josh Walrath, Jeremy Hellstrom, Allyn Malventano, and Morry Tietelman
Week in Review:
News items of interest:
Hardware/Software Picks of the Week:
Subject: Processors | May 8, 2014 - 04:26 AM | Tim Verry
Tagged: TrustZone, server, seattle, PCI-E 3.0, opteron a1100, opteron, linux, Fedora, ddr4, ARMv8, arm, amd, 64-bit
AMD showed off its first ARM-based “Seattle” processor running on a reference platform motherboard at an event in San Francisco earlier this week. The new chip, which began sampling in March, is slated for general availability in Q4 2014. The “Seattle” processor will be officially labeled the AMD Opteron A1100.
During the press event, AMD demonstrated the Opteron A1100 running on a reference design motherboard (the Seattle Development Platform). The hardware was used to drive a LAMP software stack including an ARM optimized version of Linux based on RHEL, Apache 2.4.6, MySQL 5.5.35, and PHP 5.4.16. The server was then used to host a WordPress blog that included stream-able video.
Of course, the hardware itself is the new and interesting bit and thanks to the event we now have quite a few details to share.
The Opteron A1100 features eight ARM Cortex-A57 cores clocked at 2.0 GHz (or higher). AMD has further packed in an integrated memory controller, TrustZone encryption hardware, and floating point and NEON video acceleration hardware. Like a true SoC, the Opteron A1100 supports 8 lanes of PCI-E 3.0, eight SATA III 6Gbps ports, and two 10GbE network connections.
The Seattle processor has a total of 4MB of L2 cache (each pair of cores shares 1MB of L2) and 8MB L3 cache that all eight cores share. The integrated memory controller supports DDR3 and DDR4 memory in SO-DIMM, unbuffered DIMM, and registered ECC RDIMM forms (only one type per motherboard) enabling the ARM-based platform to be used in a wide range of server environments (enterprise, SMB, and home servers et al).
AMD has stated that the upcoming Opteron A1100 processor delivers between two and four times the performance of the existing Opteron X series (which uses four x86 Jaguar cores clocked at 1.9 GHz). The A1100 has a 25W TDP and is manufactured by Global Foundries. Despite the slight increase in TDP versus the Opteron X series (the Opteron X2150 is a 22W part), AMD claims the increased performance results in notable improvements in compute/watt performance.
AMD has engineered a reference motherboard though partners will also be able to provide customized solutions. The combination of reference motherboard and ARM-based Opteron A1100 is known at the Seattle Development Platform. This reference motherboard features four registered DDR3 DIMM slots for up to 128GB of memory, eight SATA 6Gbps ports, support for standard ATX power supplies, and multiple PCI-E connectors that can be configured to run as a single PCI-E 3.0 x8 slot or two PCI-E 3.0 x4 slots.
The Opteron A1100 is an interesting move from AMD that will target low power servers. the ARM-based server chip has an uphill battle in challenging x86-64 in this space, but the SoC does have several advantages in terms of compute performance per watt and overall cost. AMD has taken the SoC elements (integrated IO, memory, companion processor hardware) of the Opteron X series and its APUs in general, removed the graphics portion, and crammed in as many low power 64-bit ARM cores as possible. This configuration will have advantages over the Opteron X CPU+GPU APU when running applications that use multiple serial threads and can take advantage of large amounts of memory per node (up to 128GB). The A1100 should excel in serving up files and web pages or acting as a caching server where data can be held in memory for fast access.
I am looking forward to the launch as the 64-bit ARM architecture makes its first major inroads into the server market. The benchmarks, and ultimately software stack support, will determine how well it is received and if it ends up being a successful product for AMD, but at the very least it keeps Intel on its toes and offers up an alternative and competitive option.
Subject: General Tech | May 7, 2014 - 06:33 PM | Jeremy Hellstrom
Tagged: arm, servers, CoreLink, CCN-508, CN-504
ARM has a new chip on the block, the CCN-508, It is a capable of combining up to eight 64-bit ARMv8 CPU clusters of four cores apiece, either all ARM Cortex-53s or ARM Cortex-57s, using ARM's AMBA 5 CHI interconnect technology. Those processors can then be attached to a wide variety of what ARM refers to as partners, including up to 24 other AMBA interconnects for other CPUs, DDR3 or DDR4 memory controllers, PCIe, SATA, and 10-40 gigabit Ethernet. So much for ARM just being a mobile processor; check out more at The Register.
"ARM has released more details about the innards of its cache-coherent on-chip networking scheme for use cases ranging from storage to servers to networking – specifically, its CCN-5xx microarchitecture family and its newest member, the muscular CoreLink CCN-508."
Here is some more Tech News from around the web:
- Danger, Will Robinson! Beware the hidden perils of BYOD @ The Register
- Amped Wireless REC15A 802.11ac Wi-Fi Range Extender Review @ Legit Reviews
- Seagate outs 2TB wireless hard drive with support for Android, iOS and Windows 8 @ The Inquirer
- 3D Printing's Success Points to a Rosy Future for Open Hardware @ Linux.com
Subject: General Tech | May 6, 2014 - 06:31 PM | Jeremy Hellstrom
Tagged: amd, arm, project skybridge, k12
The Register has put together an overview of what AMD discussed yesterday about the K12 processor and Project Skybridge. The most impressive feat is Project SkyBridge; with the license AMD now has to develop ARMv8 architecture they will be creating pin compatible ARM and x86 SoCs, so you can choose which you want to drop in your server and can easily change your mind any time in the future. The more traditional 64-bit x86 processors will be "Puma+" cores while the ARM SoCs will be 64-bit A57s, and will not only be fully HSA compliant but will be able to run Android. They also delve into AMD's upcoming strategy to remain a valid contender in the silicon ring, read on to get a glimpse into Papermaster's brain.
"AMD has announced that it will create pin-compatible 64-bit x86 and ARM SoCs in an effort it's calling "Project SkyBridge", and that it has licensed the ARMv8 architecture and will design its own home-grown ARM-based processors."
Here is some more Tech News from around the web:
- The Upcoming Windows 8.1 Apocalypse @ Slashdot
- Bill Gates: Sell off Bing? Nah. Xbox? Maybe... @ The Register
- Lenovo outs first consumer Chromebooks including Yoga-like N20p model @ The Inquirer
- Projects and Products for Maker Moms: 10 to Build and 10 to Buy @ MAKE:Blog
Subject: General Tech | May 5, 2014 - 07:46 PM | Jeremy Hellstrom
Tagged: amd, arm, seattle
While you are awaiting Josh's take on the announcements from AMD this morning you can get a brief tease at The Tech Report, who will also likely be updating their information as the presentation progresses. You can read about the chip bearing the code-name K12 here, though there is no in depth information as of yet. You can also check out the stats on a server powered by ARM Cortex-A57 CPU also known as the Opteron A1100 or Seattle. Keep your eyes peeled for more information on our front page.
"At a press event just now, AMD offered an update on its "ambidextrous" strategy for CPUs and SoCs. There's lots of juicy detail here, but the big headline news is that the company is working on two new-from-scratch CPU core designs, one that's compatible with the 64-bit ARMv8 instruction set ISA and another that is an x86 replacement for Bulldozer and its descendants."
Here is some more Tech News from around the web:
- My first foray into password management @ The Tech Report
- Building A CO2 Laser In A Hardware Store @ Hack a Day
- ARM tests: Intel flops on Android compatibility, Windows power @ The Register
- '25,000 Windows Server 2003 boxes' must be upgraded A DAY to meet OS support death date @ The Register
- Asus RT-AC68U 802.11ac Dual-Band Wireless Router @ eTeknix
- Star Wars 1313 artwork shows the canceled game's environments @ Polygon
Subject: Processors, Mobile | April 30, 2014 - 11:06 PM | Ryan Shrout
Tagged: Intel, clover trail, Bay Trail, arm, Android
While we are still waiting for those mysterious Intel Bay Trail based Android tablets to find their way into our hands, we met with ARM today to discuss quite few varying topics. One of them centered around the cost of binary translation - the requirement to convert application code compiled for one architecture and running it after conversion on a different architecture. In this case, running native ARMv7 Android applications on an x86 platform like Bay Trail from Intel.
Based on results presented by ARM, so take everything here in that light, more than 50% of the top 250 applications in the Android Play Store require binary translation to run. 23-30% have been compiled to x86 natively, 20-21% run through Dalvik and the rest have more severe compatibility concerns. That paints a picture of the current state of Android apps and the environment in which Intel is working while attempting to release Android tablets this spring.
Performance of these binary translated applications will be lower than they would be natively, as you would expect, but to what degree? These results, again gathered by ARM, show a 20-40% performance drop in games like Riptide GP2 and Minecraft while also increasing "jank" - a measure of smoothness and stutter found with variances in frame rates. These are applications that exist in a native mode but were tricked into running through binary conversion as well. The insinuation is that we can now forecast what the performance penalty is for applications that don't have a natively compiled version and are forced to run in translation mode.
The result of this is lower battery life as it requires the CPU to draw more power to keep the experience close to nominal. While gaming on battery, which most people do with items like the Galaxy Tab 3 used for testing, a 20-35% decrease in game time will hurt Intel's ability to stand up to the best ARM designs on the market.
Other downsides to this binary translation include longer load times for applications, lower frame rates and longer execution time. Of course, the Galaxy Tab 3 10.1 is based on Intel's Atom Z2560 SoC, a somewhat older Clover Trail+ design. That is the most modern currently available Android platform from Intel as we are still awaiting Bay Trail units. This also explains why ARM did not do any direct performance comparisons to any devices from its partners. All of these results were comparing Intel in its two execution modes: native and translated.
Without a platform based on Bay Trail to look at and test, we of course have to use the results that ARM presented as a placeholder at best. It is possible that Intel's performance is high enough with Silvermont that it makes up for these binary translation headaches for as long as necessary to see x86 more ubiquitous. And in fairness, we have seen many demonstrations from Intel directly that show the advantage of performance and power efficiency going in the other direction - in Intel's favor. This kind of debate requires some more in-person analysis with hardware in our hands soon and with a larger collection of popular applications.
More from our visit with ARM soon!