Samsung Completes Development of 7nm Process Technology

Subject: General Tech | April 5, 2018 - 04:06 PM |
Tagged: snapdragon 855, Semiconductor, Samsung, qualcomm, process tech, lithography, euv, 7nm, 5nm

According to an article on sedaily.com (translated) Samsung is almost six months ahead of schedule with its 7nm EUV process technology and has managed to complete the development phase as well as secure its first customer in Qualcomm. Samsung is pushing hard and fast with its process technology as it competes with TSMC and other semiconductor foundries and has invested $6 billion in a dedicated EUV line at its foundry in Hwaseong, Korea that is slated for completion in the second half of next year with production ramp-up in 2020.

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Reportedly, Samsung's first 7nm product will be a 7nm LPP (low power plus) node achieved using Extreme Ultraviolet Lithography or EUV. Samsung has set up production conditions and finalized the development of the 7nm EUV process on its Hwaseong S3 line which is located near the future site of the dedicated EUV line mentioned above. The engineers and designers that developed the 7nm process and production line have reportedly shared the design database and methodologies necessary to begin sample production for customers and have moved onto to developing Samsung's 5nm process (which is still in the early stages). Getting the EUV process up and running is an impressive feat and the expertise that Samsung is gaining will be a major breakthrough in the barrier to entry of single-digit nanometer processes.

Samsung has managed to build out 10 extreme ultraviolet lithography units and is allegedly on track to produce the Snapdragon 855 for Qualcomm towards the end of this year or early next year on its new low power 7nm process node. Note that previous reports suggested TSMC would be producing the Snapdragon 855 with SDX50 5G modem so we may have to wait to see how TSMC responds in readying production this year for confirmation on who ultimately wins Qualcomm's orders. As the node number are a bit of marketing speak (they can pick the features they want to measure for the marketing to an extent heh), Samsung notes that its 7nm process can produce dies about 40% smaller than its 10nm process. Further, the smaller process can offer 10% more performance or up to 35% more power efficiency at the same level of performance which will be a huge boost to mobile processors and products! Thanks to the smaller process node, smartphone and tablet manufacturers could produce devices with similar dimensions but larger batteries or thinner devices with the same amount of portable power (I'd vote the former, smartphones are already very thin).

Samsung hopes to press on and complete the development of its 5nm process next year and once the dedicated EUV line in Hwaseong is fully up and running in 2020 the company plans to start mass producing products for its customers on 7nm, 6nm, and 5nm processes!

In all, this is very good news for Samsung and the wider market in general as it will add competition and encourage TSMC, GLOBALFOUNDRIES, and even Intel (with its semi-custom stuff) to continue advancing what is possible and developing and refining the EUV and other even more exotic process technology methods that will be necessary for the extremely complicated and difficult problems they will face in moving beyond 5nm into 3nm and smaller nodes! We are definitely getting to a point where we will within the next decade have to figure out the once-impossible or reinvent the way we process information (e.g. quantum computing) to get things to go any faster. I am very excited and interested to see where the semiconductor industy and global computing as a whole will go from here!

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Source: SE Daily

Podcast #455 - Intel Skylake-X, AMD EPYC 7000 series, IBM 5nm, 802.11ad, and more!

Subject: General Tech | June 22, 2017 - 12:57 PM |
Tagged: video, Surface Pro, skylake-x, podcast, Intel, IBM, EPYC, amd, 802.11ad, 5nm

PC Perspective Podcast #455 - 06/22/17

Join us for talk about Intel Skylake-X, AMD EPYC 7000 series, IBM 5nm, 802.11ad, and more!

You can subscribe to us through iTunes and you can still access it directly through the RSS page HERE.

The URL for the podcast is: http://pcper.com/podcast - Share with your friends!

Hosts: Ryan Shrout, Jeremy Hellstrom, Josh Walrath, Allyn Malventano

Peanut Gallery: Alex Lustenberg, Ken Addison

Program length: 1:36:49
 
Podcast topics of discussion:
 
  1. Week in Review:
  2. News items of interest:
  3. Hardware/Software Picks of the Week
  4. Closing/outro

Subscribe to the PC Perspective YouTube Channel for more videos, reviews and podcasts!!

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IBM Announces 5nm Breakthrough with Silicon Nanosheet Technology

Subject: General Tech | June 7, 2017 - 09:31 PM |
Tagged: silicon nanosheet, Samsung, IBM, GLOBALFOUNDRIES, FinFET, 5nm

It seems only yesterday that we saw Intel introduce their 22nm FinFET technology, and now we are going all the way down to 5nm.  This is obviously an exaggeration.  The march of process technology has been more than a little challenging for the past 5+ years for everyone in the industry.  Intel has made it look a little easier by being able to finance these advances a little better than the other pure-play foundries.  It does not mean that they have not experienced challenges on their own.

We have seen some breakthroughs these past years with everyone jumping onto FinFETs with TSMC, Samsung, and GLOBALFOUNDRIES introducing their own processes.  GLOBALFOUNDRIES initially had set out on their own, but that particular endeavor did not pan out.  The ended up licensing Samsung’s 14nm processes (LPE and LPP) to start producing chips of their own, primarily for AMD in their graphics and this latest generation of Ryzen CPUs.

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These advances have not been easy.  While FinFETs are needed at these lower nodes to continue to provide the performance and power efficiency while supporting these transistor densities, the technology will not last forever.  10nm and 7nm lines will continue to use them, but many believe that while we will see the densities improve, the power characteristics will start to lag behind.  The theory is that past 7nm nodes traditional FinFETs will no longer work as desired.  This is very reminiscent of the sub 28nm processes that attempted to use planar structures on bulk silicon.  In that case the chips could be made, but power issues plagued the designs and eventually support for those process lines were dropped.

IBM and their research associates Samsung, GLOBALFOUNDRIES at SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY have announced a breakthrough in a new “Gate-All-Around” architecture made on a 5nm process.  FinFETs are essentially a rectangle surround on three sides by gates, giving it the “fin” physical characteristics.  This new technology now covers the fourth side and embeds these channels in nanosheets of silicon.

The problem with FinFETs is that they will eventually be unable to scale with power as transistors get closer and closer.  While density scales, power and performance will get worse as compared to previous nodes.  The 5nm silicon nanosheet technology gives a significant boost to power and efficiency, thereby doing to FinFETs what they did with planar structures at the 20/22nm nodes.

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One of the working EUV litho machines at SUNY Albany.

IBM asserts that the average chip the size of a fingernail can contain up to 30 billion transistors and continue to see the density, power, and efficiency improvements that we would expect with a normal process shrink.  The company expects these process nodes to start rolling out in a 2019 time frame if all goes as planned.

There are few details in how IBM was able to achieve this result.  We do know a couple things about it.  EUV lithography was used extensively to avoid the multi-patterning nightmare that this would entail.  For the past two years Ametek has been installing 100 watt EUV litho machines throughout the world to select clients.  One of these is located on the SUNY Albany campus where this research was done.  We also know that deposition was done layer by layer with silicon and the other materials.

What we don’t know is how long it takes to create a complete wafer.  Usually these test wafers are packed full of SRAM and very little logic.  It is a useful test and creates a baseline for many structures that will eventually be applied to this process.  We do not know how long it takes to produce such a wafer, but considering how the layers look to be deposited it takes a long, long time with current tools and machinery.  Cutting edge wafers in production can take upwards of 16 weeks to complete.  I hesitate to even guess how long each test wafer takes.  Because of the very 3D nature of the design, I am curious as to how the litho stages work and how many passes are still needed to complete the design.

This looks to be a very significant advancement in process technology that should be mass produced in the timeline suggested by IBM.  It is a significant jump, but it seems to borrow a lot of previous FinFET structures.  It does not encompass anything exotic like “quantum wells”, but is able to go lower than the currently specified 7nm processes that TSMC, Samsung, and Intel have hinted at (and yes, process node names should be taken with a grain of salt from all parties at this time).  IBM does appear to be comparing this to what Samsung calls its 7nm process in terms of dimensions and transistor density.

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Cross section of a 5nm transistor showing the embedded channels and silicon nanosheets.

While Moore’s Law has been stretched thin as of late, we are still seeing these scientists and engineers pushing against the laws of physics to achieve better performance and scaling at incredibly small dimensions.  The silicon nanosheet technology looks to be an effective and relatively affordable path towards smaller sizes without requiring exotic materials to achieve.  IBM and its partners look to have produced a process node that will continue the march towards smaller, more efficient, and more powerful devices.  It is not exactly around the corner, but 2019 is close enough to start planning designs that could potentially utilize this node.

Source: IBM

Honey, I shrunk the silicon

Subject: General Tech | June 5, 2017 - 12:41 PM |
Tagged: IBM, global foundries, Samsung, 5nm, 3nm. eulv, GAAFET

Extreme Ultraviolet Lithography has been the hope for reducing process size below the current size but it had not been used to create a successful 5nm chip, until now.  IBM, Samsung and GLOBALFOUNDRIES have succeeded in producing a chip using IBM's gate-all-around transistors, which will be known as GAAFETs and will likely replace the current tri-gate FinFETs used today.  A GAAFET resembles a FinFET rotated 90 degrees so that the channels run horizontally, stacked three layers high with gates filling in the gaps, hence the name chosen. 

Density will go up, this process will fit 30 billion transistors in a 50mm2 chip, 50% more than the previous best commercial process and performance can be increased by 40% at the same power as our current chips or offer the same performance while consuming 75% less power.  Ars Technica delves into the technology required to make GAAFETs and more of the potential in their article.

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"IBM, working with Samsung and GlobalFoundries, has unveiled the world's first 5nm silicon chip. Beyond the usual power, performance, and density improvement from moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA) transistors, and the first real use of extreme ultraviolet (EUV) lithography."

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Source: Ars Technica