GLOBALFOUNDRIES Technical Conference Releases

Subject: General Tech | September 20, 2017 - 09:44 PM |
Tagged: GLOBALFOUNDRIES, FinFET, FD-SOI, 12nm, 14nm, 14nm+, 22FDX, 28FDX, 12FDX, amd, Vega, ryzen

The day after Intel had its Technology and Manufacturing expo in China, GLOBALFOUNDRIES kicks off their own version of the event and has made a significant number of announcements concerning upcoming and next generation process technologies. GF (GLOBALFOUNDRIES) had been the manufacturing arm of AMD until it was spun off as its own entity in 2009. Since then GF has been open to providing fabless semiconductor firms a viable alternative to TSMC and other foundries. Their current 14nm process is licensed from Samsung, as GF had some significant issues getting their own version of that technology into production. GF looks to be moving past their process hiccups in getting to FinFET technologies as well as offering other more unique process nodes that will serve upcoming mobile technologies very well.
 
GloFoundries_logo.jpg
 
The big announcement today was the existence of the 12LP process. This is a "12 nm" process that looks to be based off of their previous 14nm work. It is a highly optimized variant that offers around 15% better density and 10% better performance than current 14/16nm processes from competing firms. Some time back GF announced that it would be skipping the 10nm node and going directly to 7nm, but it seems that market forces have pushed them to further optimize 14nm and offer another step.  Regular process improvement cadences are important to fabless partners as they lay out their roadmaps for future products.
 
12FP is also on track to be Automotive Grade 2 Certified by Q4 2017, which opens it up to a variety of automotive applications. Self-driving cars are the hot topic these days and it appears as though GF will be working with multiple manufacturers including Tesla. The process also has an RF component that can be utilized for those designs.
 
There had been some questions before this about what GF would do between 14nm and their expected 7nm offering. AMD had previously shown a roadmap with the first generation Zen being offered on 14nm and a rather nebulous sounding 14nm+ process. We now know that 12LP is going to be the process that AMD leverages for Zen and Vega refreshes next year. GF is opening up risk production in 1H 2018 for early adopters. This typically means that tuning is still going on with the process, and wafer agreements tend to not hinge on "per good die". Essentially, just as the wording suggest, the monetary risks of production fall more on the partner rather than the foundry. I would expect the Zen/Vega refreshes to start rolling out mid-Summer 2018 if all goes well with 12LP.
 
GF-FAB.jpg
 
RF is getting a lot of attention these days. In the past I had talked quite a bit about FD-SOI and the slow adoption of that technology. In the 5G world that we are heading to, RF is becoming far more important. Currently GF has their 28FDX and 22FDX processes which utilize FD-SOI (Fully Depleted Silicon On Insulator). 22FDX is a dual purpose node that can handle both low-leakage ASICs as well as RF enabled products (think cell-phone modems). GF has also announced a new RF centric process node called 8SW SOI. This is a 300mm wafer based technology at Fab 10 located in East Fishkill, NY. This was once an IBM fab, but was eventually "given" to GF for a variety of reasons. The East Fishkill campus is also a center for testing and advanced process development.
 
22FDX is not limited to ASIC and RF production. GF is announcing that it is offering eMRAM (embedded magnetoresistive non-volatile memory) support. GF claims that ic an retain data through a 260C solder reflow while retaining data for more than 10 years at 125C. These products were developed through a partnership with Everspin Technologies. 1Gb DDR MRAM chips have been sampled and 256Mb DDR MRAM chips are currently available through Everspin. This technology is not limited to standalone chips and can be integrated into SOC designs utilizing eFlash and SRAM interface options.
 
GLOBALFOUNDRIES has had a rocky start since it was spun off from AMD. Due to aggressive financing from multiple sources it has acquired other pure play foundries and garnered loyal partners like AMD who have kept revenue flowing. If GF can execute on these new technologies they will be on a far more even standing with TSMC and attract new customers. GF has the fab space to handle a lot of wafers, but these above mentioned processes could be some of their first truly breakthrough products that differentiates itself from the competition.

Raven Ridge rumours

Subject: General Tech | September 18, 2017 - 04:17 PM |
Tagged: amd, raven ridge, Bristol Ridge, Ryzen 5 2500U, Zen, Vega, 14nm

If the rumours are true, the new 14nm Raven Ridge based AMD Ryzen 5 2500U will offer an impressive jump in performance compared to AMD's current generation of APUs.  The Inquirer's source suggests the new APU will offer a 50% jump in single threaded performance and an impressive 90% advantage on multi-threaded performance.  The multithreaded performance improvement may be the headline but seeing a huge increase in single threaded applications, AMD's recent Achilles Heel, shows some interesting improvements to Zen.  This will also mark the arrival of their first APU with Vega onboard, so you can expect better graphics performance as well.  The benchmark numbers and links are here.

raven_ridge_3.jpg

"LEAKED BENCHMARKS for AMD's forthcoming Raven Ridge APUs suggest that upcoming devices, expected to be launched in time for Christmas, will outperform current Bristol Ridge APUs by up to 90 per cent on multicore applications."

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Tech Talk

Source: The Inquirer

Samsung Announces 11nm LPP and 7nm LPP Processes

Subject: General Tech | September 11, 2017 - 05:27 PM |
Tagged: Vega, TSMC, Samsung, ryzen, Intel, euv, 8nm, 7nm, 14nm, 11nm, 10nm

Process technology is extremely complex today, and getting more and more complex by the minute.  The billions of dollars invested in each process node essentially insures that it will have to be used for years to come to get back that investment.  It not only needs to get back that investment, but provide more funds to start R&D on the next series of nodes that will come down the line.  It has only been a couple of years since the introduction of multiple 14nm processes from Intel and Samsung, as well as the 16nm node from TMSC.  We are already moving towards an introduction of 10nm parts from these manufacturers in bulk starting next year.  So have these manufacturers gotten their money worth out of their current processes?
 
Samsung-Foundry-Forum2017_main_1.jpg
 
Kinam Kim, President of Samsung Electronics’ Semiconductor Business, discloses the latest process advances from his division.
 
Part of that answer somes in the form of Samsung's latest product.  Samsung is announcing the availability of a new 11nm FinFET process that looks to be a pretty extensive optimization of the company's 14nm FF.  The new process promises 15% better performance and 10% chip area reduction at the same power consumption as the older 14nm FF.  The idea here is to further improve upon their 14nm process all the while retaining the economics of it.  This process exists separately from the latest 10nm LPP which can be considered a full jump from the previous 14nm.  11nm LPP will be primarily aimed at midrange and high end products, but will not reach the full scaling and performance of the 10nm LPP product.
 
This "little steps" philosophy has been around for ages, as AMD utilized it for most of their existence when they owned their own Fabs.  Other companies have done the same by including small improvements over the lifetime of the process so that the final product is signficantly better in terms of yield, transistor switching speed, and thermal dissipation.  Samsung looks to be doing this with their 11nm process by providing all those little steps of improvement from 14nm.
 
The second part of the announcement is that Samsung has announced their 7nm process using EUV.  Samsung had previously announced their 8nm process, but it still relies upon multi-patterning immersion litho.  Samsung has been testing their 250 watt EUV source with fairly good results.  The company is quoted as to processing over 200,000 wafers since 2014 and has achieved an 80% yeild on 256 Mb SRAM.  This is somewhat impressive, but still not ready for primetime.  SRAM features highly consistent structures and is typically one of the first complex chips tested on a new process.
 
Samsung is offering orders now of its 11nm line and it will be very interesting to see who jumps on board.  I would not expect AMD to transfer their designs to 11nm, as a tremendous amount of reworking and validating are required. Instead we will see AMD going for the 10nm node with their Zen 2 based products while continuing to produce Ryzen, Vega, and Polaris at 14nm. Those that will be taking advantage of 11nm will probably be groups pushing out smaller products, especially for the midrange and high end cell phone SOCs.
 
10nm LPP is expected in early 2018, 8nm LPP in 2019, and finally Samsung hopes for 7nm to be available in 2020.
Source: Samsung

Details on Intel's Gemini Lake SoC Leak: A Refined Apollo Lake Coming Soon

Subject: Processors | May 31, 2017 - 02:33 PM |
Tagged: Intel, goldmont+, gemini lake, apollo lake, 14nm

Information recently leaked on the successor to Intel’s low power Apollo Lake SoCs dubbed Gemini Lake. Several sites via FanlessTech claim that Gemini Lake will launch by the end of the year and will be the dual and quad core processors used to power low cost notebooks, tablets, 2-in-1 convertibles, and SFF desktop and portable PCS.

Intel-2016-2017-Processor-Roadmap-Kaby-Lake-Coffee-Lake-Cannonlake.jpg

A leaked Intel roadmap.

Gemini Lake appears to be more tick than tock in that it uses a similar microarchitecture as Apollo Lake and relies mainly on process node improvements with the refined 14nm+ process to increase power efficiency and performance per watt. On the CPU side of things, Gemini Lake utilizes the Goldmont+ microarchitecture and features two or four cores paired with 4MB of L2 cache. Intel has managed to wring higher clockspeeds while lowering power draw out of the 14nm process. A doubling of the L2 cache versus Apollo Lake will certainly give the chip a performance boost. The SoC will use Intel Gem9 graphics with up to 18 Execution Units (similar to Apollo Lake) but the GPU will presumably run at higher clocks. Additionally, the Gemini Lake SoC will integrate a new single channel DDR4 memory controller that will support higher memory speeds, s WLAN controller (a separate radio PHY is still required on the motherboard) supporting 802.11 b/g/n and Bluetooth 4.0.

Should the leaked information turn out to be true, he new Gemini Lake chips are shaping up to be a good bit faster than their predecessor while sipping power with TDPs of up to 6W for mobile devices and 10W for SFF desktop.

The lower power should help improve battery life a bit which is always a good thing. And if they can pull off higher performance as well all the better!

Unfortunately, it is sounding like Gemini Lake will not be ready in te for the back to school or holiday shopping seasons this year. I expect to see a ton of announcements on devices using the new SoCs at CES though!

Also read:

 

Source:

Intel is proud of its tiny sized FinFET

Subject: General Tech | March 30, 2017 - 01:20 PM |
Tagged: Intel, 14nm, 14 nm FinFET

At Intel's Technology and Manufacturing Day event in San Francisco there was a lot of talk about how Intel's 14nm process technology compares to the 16nm, 14nm, and 10nm offerings of their competitors.  Investors and enthusiasts are curious if Intel can hold their lead in process tech as Samsung seems to be on track to release chips fabbed on 10nm process before Intel will.  Intel rightly pointed out that not all process tech is measured the same way and that pitch measurements give only one part of the picture; meaning Samsung might not actually be smaller than them.

The Tech Report were present at that meeting and have written up an in depth look at what Intel means when they dispute the competitions claims, as well as their rationale behind their belief that the 14nm node still has a lot of life left in it.

14nmcomparo.png

"As process sizes grow smaller and smaller, Intel believes that the true characteristics of those technology advances are being clouded by an over-reliance on a single nanometer figure. At its Technology and Manufacturing Day this week, the company defended its process leadership and proposed fresh metrics that could more accurately describe what a given process is capable of."

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Three Kaby Lakes for three Z270s; it's an overclocking menage a trois

Subject: Processors | January 3, 2017 - 03:54 PM |
Tagged: z270, overclocking, kaby lake, Intel, i7-7700k, core i7-7700k, 7th generation core, 7700k, 14nm

Having already familiarized yourself with Intel's new Kaby Lake architecture and the i7-7700k processor in Ryan's review you may now be wondering how well the new CPU overclocks for others.  [H]ard|OCP received three i7-7700k's and three different Z270 motherboards for testing and they set about overclocking these in combination to see what frequency they could reach.  Only one of the chips was ever stable at 5GHz, and it is reassuring that it managed that on all three motherboards, the remaining two would only hit 4.8GHz which is still not a bad result.  Drop by to see their settings in full detail.

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"After having a few weeks to play around with Intel's new Kaby Lake architecture Core i7-7700K processors, we finally have some results that we want to discuss when it comes to overclocking and the magic 5GHz many of us are looking for, and what we think your chances are of getting there yourself."

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Processors

Source: [H]ard|OCP
Author:
Subject: Processors
Manufacturer: Intel

Architectural Background

It probably doesn't surprise any of our readers that there has been a tepid response to the leaks and reviews that have come out about the new Core i7-7700K CPU ahead of the scheduled launch of Kaby Lake-S from Intel. Replacing the Skylake-based 6700K part as the new "flagship" consumer enthusiast CPU, the 7700K has quite a bit stacked against it. We know that Kaby Lake is the first in the new sequence of tick-tock-optimize, and thus there are few architectural changes to any portion of the chip. However, that does not mean that the 7700K and Kaby Lake in general don't offer new capabilities (HEVC) or performance (clock speed). 

The Core i7-7700K is in an interesting spot as well with regard to motherboards and platforms. Nearly all motherboards that run the Z170 chipset will be able to run the new Kaby Lake parts without requiring an upgrade to the newly released Z270 chipset. However, the likelihood that any user on a Z170 platform today using a Skylake processor will feel the NEED to upgrade to Kaby Lake is minimal, to say the least. The Z270 chipset only offers a couple of new features compared to last generation, so the upgrade path is again somewhat limited in excitement.

Let's start by taking a look at the Core i7-7700K and how it compares to the previous top-end parts from the consumer processor line and then touch on the changes that Kaby Lake brings to the table.

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With the beginning of CES just days away (as I write this), Intel is taking the wrapping paper off of its first gift of 2017 to the industry. As you can see from the slide above, more than just the Kaby Lake-S consumer socketed processors are launching today, but other components including Iris Plus graphics implementations and quad-core notebook implementations will need to wait for another day.

slides10.jpg

For DIY builders and OEMs, Kaby Lake-S, now known as the 7th Generation Core Processor family, offer some changes and additions. First, we will get a dual-core HyperThreaded processor with an unlocked designation in the Core i3-7350K. Other than the aforementioned Z270 chipset, Kaby Lake will be the first platform compatible with Intel Optane memory. (To be extra clear, I was told that previous processors will NOT be able to utilize Optane in its M.2 form factor.)

slides11.jpg

Though we have already witnessed Lenovo announcing products using Optane, this is the first official Intel discussion about it. Optane memory will be available in M.2 modules that can be installed on Z270 motherboards, improving snappiness and responsiveness. It seems this will be launched later in the quarter as we don't have any performance numbers or benchmarks to point to demonstrating the advantages that Intel touts. I know both Allyn and I are very excited to see how this differs from previous Intel caching technologies.

  Core i7-7700K Core i7-6700K Core i7-5775C Core i7-4790K Core i7-4770K Core i7-3770K
Architecture Kaby Lake Skylake Broadwell Haswell Haswell Ivy Bridge
Process Tech 14nm+ 14nm 14nm 22nm 22nm 22nm
Socket LGA 1151 LGA 1151 LGA 1150 LGA 1150 LGA 1150 LGA 1155
Cores/Threads 4/8 4/8 4/8 4/8 4/8 4/8
Base Clock 4.2 GHz 4.0 GHz 3.3 GHz 4.0 GHz 3.5 GHz 3.5 GHz
Max Turbo Clock 4.5 GHz 4.2 GHz 3.7 GHz 4.4 GHz 3.9 GHz 3.9 GHz
Memory Tech DDR4 DDR4 DDR3 DDR3 DDR3 DDR3
Memory Speeds Up to 2400 MHz Up to 2133 MHz Up to 1600 MHz Up to 1600 MHz Up to 1600 MHz Up to 1600 MHz
Cache (L4 Cache) 8MB 8MB 6MB (128MB) 8MB 8MB 8MB
System Bus DMI3 - 8.0 GT/s DMI3 - 8.0 GT/s DMI2 - 6.4 GT/s DMI2 - 5.0 GT/s DMI2 - 5.0 GT/s DMI2 - 5.0 GT/s
Graphics HD Graphics 630 HD Graphics 530 Iris Pro 6200 HD Graphics  4600 HD Graphics 4600 HD Graphics  4000
Max Graphics Clock 1.15 GHz 1.15 GHz 1.15 GHz 1.25 GHz 1.25 GHz 1.15 GHz
TDP 91W 91W 65W 88W 84W 77W
MSRP $339 $339 $366 $339 $339 $332

Continue reading our review of the Intel Core i7-7700K Kaby Lake processor!!

Samsung Has Announcements for 14nm, 10nm, and 7nm

Subject: General Tech | November 5, 2016 - 07:01 AM |
Tagged: Samsung, euv, 7nm, 14nm, 10nm

As the comments usually remind us, the smallest feature size varies in interpretation from company to company, and node to node. You cannot assume how Samsung compares with Intel, GlobalFoundries, or TSMC based on the nanometer rating alone, better or worse. In fact, any specific fabrication process, when compared to another one, might be better in some ways yet worse in others.

samsung-logo.png

With all of that in mind, Samsung has announced the progress they've made with 14nm, 10nm, and 7nm fabrication processes. First, they plan to expand 14nm production with 14LPU. I haven't been able to figure out what this specific branding stands for, but I'm guessing it's something like “Low Power Ultra” given that it's an engineering name and those are usually super literal (like the other suffixes).

As for the other suffixes, Samsung begins manufacturing nodes with Low Power Early (LPE). From there, they improve upon their technique, providing higher performance and/or lower power, and call this new process Low Power Plus (LPP). LPC, which I believe stands for something like Low Power Cost, although I haven't seen this acronym officially expanded, removes a few manufacturing steps to make the end product cheaper. LPU is an extension of LPC with higher performance. Add the appropriate acronym as a suffix to the claimed smallest feature size, and you get the name of the node: xxLPX.

14LPU is still a ways out, though. Their second announcement, 10LPU, is expected to be their cost-reduction step for 10nm, which I interpret to mean they are omitting LPC from their 10nm production. You may think this is very soon, given how 10LPE has just started mass production a few weeks ago. Really, this is a quite early announcement in terms of overall 10nm production. The process design kits (PDKs) for both 14LPU and 10LPU, which are used by hardware vendors to design their integrated circuits, won't ship until 2Q17. As such, products will be a while behind that.

To close out, Samsung reiterated that 7nm is planned to use extreme ultraviolet lithography (EUV). They have apparently created a wafer using 7nm EUV, but images do not seem to be provided.

Development kits for 14LPU and 10LPU are expected to ship in the second quarter of 2017.

Source: Samsung

IBM Prepares Power9 CPUs to Power Servers and Supercomputers In 2018

Subject: Processors | September 2, 2016 - 01:39 AM |
Tagged: IBM, power9, power 3.0, 14nm, global foundries, hot chips

Earlier this month at the Hot Chips symposium, IBM revealed details on its upcoming Power9 processors and architecture. The new chips are aimed squarely at the data center and will be used for massive number crunching in big data and scientific applications in servers and supercomputer nodes.

Power9 is a big play from Big Blue, and will help the company expand its precense in the Intel-ruled datacenter market. Power9 processors are due out in 2018 and will be fabricated at Global Foundries on a 14nm HP FinFET process. The chips feature eight billion transistors and utilize an “execution slice microarchitecture” that lets IBM combine “slices” of fixed, floating point, and SIMD hardware into cores that support various levels of threading. Specifically, 2 slices make an SMT4 core and 4 slices make an SMT8 core. IBM will have Power9 processors with 24 SMT4 cores or 12 SMT8 cores (more on that later). Further, Power9 is IBM’s first processor to support its Power 3.0 instruction set.

IBM Power9.jpg

According to IBM, its Power9 processors are between 50% to 125% faster than the previous generation Power8 CPUs depending on the application tested. The performance improvement is thanks to a doubling of the number of cores as well as a number of other smaller improvements including:

  • A 5 cycle shorter pipeline versus Power8
  • A single instruction random number generator (RNG)
  • Hardware assisted garbage collection for interpreted languages (e.g. Java)
  • New interrupt architecture
  • 128-bit quad precision floating point and decimal math support
    • Important for finance and security markets, massive databases and money math.
    • IEEE 754
  • CAPI 2.0 and NVLink support
  • Hardware accelerators for encryption and compression

The Power9 processor features 120 MB of direct attached eDRAM that acts as an L3 cache (256 GB/s). The chips offer up 7TB/s of aggregate fabric bandwidth which certainly sounds impressive but that is a number with everything added together. With that said, there is a lot going on under the hood. Power9 supports 48 lanes of PCI-E 4.0 (2 GB/s per lane per direction), 48 lanes of proprietary 25Gbps accelerator lanes – these will be used for NVLink 2.0 to connect to NVIDIA GPUs as well as to connect to FPGAs, ASICs, and other accelerators or new memory technologies using CAPI 2.0 (Coherent Accelerator Processor Interface) – , and four 16Gbps SMP links (NUMA) used to combine four quad socket Power9 boards into a single 16 socket “cluster.”

These are processors that are built to scale and tackle the big data problems. In fact, not only is Google interested in Power9 to power its services, but the US Department of Energy will be building two supercomputers using IBM’s Power9 CPUs and NVIDI’s Volta GPUs. Summit and Sierra will offer between 100 to 300 Petaflops of computer power and will be installed at Oak Ridge National Laboratory and Lawrence Livermore National Laboratory respectively. There, some of the projects they will tackle is enabling the researchers to visualize the internals of a virtual light water reactor, research methods to improve fuel economy, and delve further into bioinformatics research.

The Power9 processors will be available in four variants that differ in the number of cores and number of threads each core supports. The chips are broken down into Power9 SO (Scale Out) and Power9 SU (Scale Up) and each group has two processors depending on whether you need a greater number of weaker cores or a smaller number of more powerful cores. Power9 SO chips are intended for multi-core systems and will be used in servers with one or two sockets while Power9 SU chips are for multi-processor systems with up to four sockets per board and up to 16 total sockets per cluster when four four socket boards are linked together. Power9 SO uses DDR4 memory and supports a theoretical maximum 4TB of memory (1TB with today’s 64GB DIMMS) and 120 GB/s of bandwidth while Power9 SU uses IBM’s buffered “Centaur” memory scheme that allows the systems to address a theoretical maximum of 8TB of memory (2TB with 64GB DIMMS) at 230 GB/s. In other words, the SU series is Big Blue’s “big guns.”

Power9 SO Die Shot Photo.jpg

A photo of the 24 core SMT4 Power9 SO die.

Here is where it gets a bit muddy. The processors are further broken down by an SMT4 or SMT8 and both Power9 SO and Power9 SU have both options. There are Power9 CPUs with 24 SMT4 cores and there are CPUs with 12 SMT8 cores. IBM indicated that SMT4 (four threads per core) was suited to systems running Linux and virtualization with emphasis on high core counts. Meanwhile SMT8 (eight threads per core) is a better option for large logical partitions (one big system versus partitioning out the compute cluster into smaller VMs as above) and running IBM’s Hypervisor. In either case (24 SMT4 or 12 SMT8) there is the same number of total threads, but you are able to choose whether you want fewer “stronger” threads on each core or more (albeit weaker) threads per core depending on which you workloads are optimized for.

Servers supporting Power9 are already under development by Google and Rackspace and blueprints are even available from the OpenPower Foundation. Currently, it appears that Power9 SO will emerge as soon as the second half of next year (2H 2017) with Power9 SU following in 2018 which would line up with the expected date for the Summit and Sierra supercomputer launches.

This is not a chip that will be showing up in your desktop any time soon, but it is an interesting high performance processor! I will be keeping an eye on updates from Oak Ridge lab hehe.

Intel Will Release 14nm Coffee Lake To Succeed Kaby Lake In 2018

Subject: Processors | July 28, 2016 - 02:47 PM |
Tagged: kaby lake, Intel, gt3e, coffee lake, 14nm

Intel will allegedly be releasing another 14nm processor following Kaby Lake (which is itself a 14nm successor to Skylake) in 2018. The new processors are code named "Coffee Lake" and will be released alongside low power runs of 10nm Cannon Lake chips. 

Intel Coffe Lake to Coexist With Cannon Lake.jpg

Not much information is known about Coffee Lake outside of leaked slides and rumors, but the first processors slated to launch in 2018 will be mainstream mobile chips that will come in U and HQ mobile flavors which are 15W to 28W and 35W to 45W TDP chips respectively. Of course, these processors will be built on a very mature 14nm process with the usual small performance and efficiency gains beyond Skylake and Kaby Lake. The chips should have a better graphics unit, but perhaps more interesting is that the slides suggest that Coffee Lake will be the first architecture where Intel will bring "hexacore" (6 core) processors into mainstream consumer chips! The HQ-class Coffee Lake processors will reportedly come in two, four, and six core variants with Intel GT3e class GPUs. Meanwhile the lower power U-class chips top out at dual cores with GT3e class graphics. This is interesting because Intel has previous held back the six core CPUs for its more expensive and higher margin HEDT and Xeon platforms.

Of course 2018 is also the year for Cannon Lake which would have been the "tock" in Intel's old tick-tock schedule (which is no more) as the chips will move to a smaller process node and then Intel would improve on the 10nm process from there in future architectures. Cannon Lake is supposed to be built on the tiny 10nm node, and it appears that the first chips on this node will be ultra low power versions for laptops and tablets. Occupying the ULV platform's U-class (15W) and Y-class (4.5W), Cannon Lake CPUs will be dual cores with GT2 graphics. These chips should sip power while giving comparable performance to Kaby and Coffee Lake perhaps even matching the performance of the Coffee Lake U processors!

Stay tuned to PC Perspective for more information!