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Intel Core i5-3470 Ivy Bridge Processor and HD 2500 Graphics Review

Author:
Date: June 26, 2012
Subject: Processors
Manufacturer: Intel
Tagged: Ivy Bridge, Intel, i5-3470

A slightly lower cost Ivy Bridge

Just a couple of short months ago, Intel released the desktop versions of its latest CPU architecture codenamed Ivy Bridge – and officially named the Intel 3rd Generation Core Processor. Ivy Bridge has a much cleaner sound to it if you ask me.  

At launch, we tested and reviewed the highest-end offering, the Core i7-3770K, a quad-core HyperThreaded part that runs as fast as 3.9 GHz with Turbo Boost. It included the highest end processor graphics Intel has developed – the HD 4000. Currently selling for only $350, the i7-3770K is a fantastic processor, but isn't the bargain that many DIY PC builders are looking for. The new Core i5-3470 from Intel – the processor we are reviewing today – might be just that.

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I am not going to spend time discussing the upgrades and benefits that the new Ivy Bridge processors offer over their predecessors, or the competition, from an architectural stand point. If you want some background on Ivy Bridge and why it does what it does, you'll want to read the first few pages of our original Core i7-3770K / Ivy Bridge review from April. 

The Core i5-3470 Processor

Interestingly, in the initial information from Intel about the Ivy Bridge processor lineup, the Core i5-3470 wasn't even on the list. There was a 3450 and 3550, but nothing in between. The Core i5-3470 currently sells for about $200 and compares with some other Ivy Bridge processors with the following specifications:

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Continue reading our review of the Intel Core i5-3470 Ivy Bridge and HD 2500 Processor!!

Intel Introduces Xeon Phi: Larrabee Unleashed

Subject: Processors | June 19, 2012 - 11:46 AM |
Tagged: Xeon Phi, xeon e5, nvidia, larrabee, knights corner, Intel, HPC, gpgpu, amd

Intel does not respond well when asked about Larabee.  Though Intel has received a lot of bad press from the gaming community about what they were trying to do, that does not necessarily mean that Intel was wrong about how they set up the architecture.  The problem with Larrabee was that it was being considered as a consumer level product with an eye for breaking into the HPC/GPGPU market.  For the consumer level, Larrabee would have been a disaster.  Intel simply would not have been able to compete with AMD and NVIDIA for gamers’ hearts.
 
The problem with Larrabee and the consumer space was a matter of focus, process decisions, and die size.  Larrabee is unique in that it is almost fully programmable and features really only one fixed function unit.  In this case, that fixed function unit was all about texturing.    Everything else relied upon the large array of x86 processors and their attached vector units.  This turns out to be very inefficient when it comes to rendering games, which is the majority of work for the consumer market in graphics cards.  While no outlet was able to get a hold of a Larrabee sample and run benchmarks on it, the general feeling was that Intel would easily be a generation behind in performance.  When considering how large the die size would have to be to even get to that point, it was simply not economical for Intel to produce these cards.
 
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Xeon Phi is essentially an advanced part based on the original Larrabee architecture.
 
This is not to say that Larrabee does not have a place in the industry.  The actual design lends itself very nicely towards HPC applications.  With each chip hosting many x86 processors with powerful vector units attached, these products can provide tremendous performance in HPC applications which can leverage these particular units.  Because Intel utilized x86 processors instead of the more homogenous designs that AMD and NVIDIA use (lots of stream units doing vector and scalar, but no x86 units or a more traditional networking fabric to connect them).  This does give Intel a leg up on the competition when it comes to programming.  While GPGPU applications are working with products like OpenCL, C++ AMP, and NVIDIA’s CUDA, Intel is able to rely on many current programming languages which can utilize x86.  With the addition of wide vector units on each x86 core, it is relatively simple to make adjustments to utilize these new features as compared to porting something over to OpenCL.
 
So this leads us to the Intel Xeon Phi.  This is the first commercially available product based on an updated version of the Larrabee technology.  The exact code name is Knights Corner.  This is a new MIC (many integrated cores) product based on Intel’s latest 22 nm Tri-Gate process technology.  The details are scarce on how many cores this product actually contains, but it looks to be more than 50 of a very basic “Pentium” style core;  essentially low die space, in-order, and all connected by a robust networking fabric that allows fast data transfer between the memory interface, PCI-E interface, and the cores.
 
intelphi.jpg
 
Each Xeon Phi promises more than 1 TFLOP of performance (as measured by Linpack).  When combined with the new Xeon E5 series of processors, these products can provide a huge amount of computing power.  Furthermore, with the addition of the Cray interconnect technology that Intel acquired this year, clusters of these systems could provide for some of the fastest supercomputers on the market.  While it will take until the end of this year at least to integrate these products into a massive cluster, it will happen and Intel expects these products to be at the forefront of driving performance from the Petascale to the Exascale.
 
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These are the building blocks that Intel hopes to utilize to corner the HPC market.  Providing powerful CPUs and dozens if not hundreds of MIC units per cluster, the potential computer power should bring us to the Exascale that much sooner.
 
Time will of course tell if Intel will be successful with Xeon Phi and Knights Corner.  The idea behind this product seems sound, and the addition of powerful vector units being attached to simple x86 cores should make the software migration to massively parallel computing just a wee bit easier than what we are seeing now with GPU based products from AMD and NVIDIA.  The areas that those other manufacturers have advantages over Intel are that of many years of work with educational institutions (research), software developers (gaming, GPGPU, and HPC), and industry standards groups (Khronos).  Xeon Phi has a ways to go before being fully embraced by these other organizations, and its future is certainly not set in stone.  We have yet to see 3rd party groups get a hold of these products and put them to the test.  While Intel CPUs are certainly class leading, we still do not know of the full potential of these MIC products as compared to what is currently available in the market.
 

The one positive thing for Intel’s competitors is that it seems their enthusiasm for massively parallel computing is justified.  Intel just entered that ring with a unique architecture that will certainly help push high performance computing more towards true heterogeneous computing. 

Source: Intel

Live Blog: AMD Fusion Developer Summit 2012 (AFDS)

Subject: Graphics Cards, Processors, Shows and Expos | June 14, 2012 - 11:46 AM |
Tagged: live blog, arm, APU, amd, AFDS

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Day 3 - Thursday, June 14th

We are here at AFDS 2012 for the day 3 keynotes - join us as find out what else AMD has in store.  

If you are looking for Tuesday or Wednesday keynotes and information on the announcement of the HSA Foundation, you can find it below, after the break!

Source: PC Perspective

AMD Licenses ARM Technology: AMD Leans on ARM for Security

Subject: Processors | June 13, 2012 - 10:00 AM |
Tagged: TrustZone, hsa, Cortex-A5, cortex, arm, APU, amd, AFDS

Last year after that particular AFDS, there was much speculation that AMD and ARM would get a whole lot closer.  Today we have confirmed that in two ways.  The first is that AMD and ARM are founding members of the HSA Foundation.  This endeavor is a rather ambitious project that looks to make it much easier for programmers to access the full computer power of a CPU/GPU combo, or as AMD likes to call them, the APU.  The second confirmation is one that has been theorized for quite some time, but few people have actually hit upon the actual implementation.  This second confirmation is that AMD is licensing ARM cores and actually integrating them into their x86 based APUs.

HSAFoundation-FINAL-Desktop.png
 
AMD and ARM are serious about working with each other.  This is understandable as both of them are competing tooth and nail with Intel.
 
ARM has a security functionality that they have been working with for several years now.  This is called ARM TrustZone.  It is a set of hardware and software products that provide a greater amount of security in data transfer and transactions.  The hardware basis is built into the ARM licensed designs and is implemented in literally billions of devices (not all of them enabled).  The biggest needs that this technology addresses are that of secure transactions and password enabled logins.  Money is obviously quite important, but with identity theft and fraud on the rise, secure logins to personal information or even social sites are reaching the same level of importance as large monetary transactions.
 
AMD will actually be implementing a Cortex-A5 processor into AMD APUs that will handle the security aspects of ARM TrustZone.  The A5 is the smallest Cortex processor available, and that would make sense to use it in a full APU so it will not take up an extreme amount of die space.  When made on what I would assume to be a 28 nm process, a single A5 processor would likely take up as little as 10 to 15 mm squared of space on the die.
 
This is not exactly the licensing agreement that many analysts had expected from AMD.  It is a start though.  I would generally expect AMD to be more aggressive in the future with offerings based on ARM technologies.  If we remember some time ago Rory Read of AMD pronounced their GPU technology as “the crown jewel” of their IP lineup, it makes little sense for AMD to limit this technology just to standalone GPUs and x86 based APUs.  If AMD is serious about heterogeneous computing, I would expect them to eventually move into perhaps not the handheld ARM market initially, but certainly with more server level products based on 64 bit ARM technology.
 
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Cortex-A5: coming to an AMD APU near you in 2013/2014.  Though probably not in quad core fashion as shown above.
 
AMD made a mistake once by selling off their ultra-mobile graphics group, Imageon.  This was sold off to Qualcomm, who is now a major player in the ARM ecosystem with their Snapdragon products based on Adreno graphics (“Adreno” is an anagram of “Radeon”).  With the release of low powered processors in both the Brazos and Trinity line, AMD is again poised to deliver next generation graphics to the low power market.  Now the question is, what will that graphics unit be attached to?
 
 
Source: AMD

AFDS 2012: HSA Foundation Joins AMD, ARM, Ti, Imagination and MediaTek with Open Architecture

Subject: Graphics Cards, Processors | June 12, 2012 - 01:31 PM |
Tagged: texas instruments, mediatek, imagination, hsa foundation, hsa, arm, amd, AFDS

Today is a big day for AMD as they, along with four other major players in the world of processors and SoCs, announced the formation of the HSA Foundation.  The HSA Foundation is a non-profit consortium created to define and promote an open approach to heterogeneous computing.  The primary goal is to make it easier for software developers to write and program for the parallel power of GPUs.  This encompasses both integrated and discrete of which the HSA (heterogeneous systems architecture) Foundation wants to enable users to take full advantage of all the processing resources available to them.

On stage at the AMD Fusion Developer Summit in Bellevue, WA, AMD announced the formation of the consortium in partnership with ARM, Imagination Technologies, MediaTek, and Texas Instruments; some of the biggest names in computing. 

The companies will work together to drive a single architecture specification and simplify the programming model to help software developers take greater advantage of the capabilities found in modern central processing units (CPUs) and graphics processing units (GPUs), and unlock the performance and power efficiency of the parallel computing engines found in heterogeneous processors.

HSA Foundation_Logo.png

There are a lot of implications in this simple statement and there are many questions that are left open ended to which we hope to get answered this week while at AFDS.  The idea of a "single architecture specification" set a lot of things in motion and makes us question the direction of both AMD and the traditionally ARM-based companies of the HSA Foundation will be moving in.  AMD has had the APU, and the eventual complete fusion of the CPU and GPU, on its roadmap for quite a few years and has publicly stated that in 2014 they will have their first fully HSA-capable part.  We are still assuming that this is an x86 + Radeon based part, but that may or may not be the long term goal; ideas of ARM-based AMD processors with Radeon graphics technology AND of Radeon based ARM-processors built by other companies still swirl amongst the show.  There are even rumors of Frankenstein-like combinations of x86 and ARM based products for niche applications.

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Looks like there is room for a few more founding partners...

Obviously ARM and others have their own graphics IP (ARM has Mali, Imagination Technology has Power VR) and those GPUs can be used for parallel processing in much the same way that we think of GPU processing on discrete GPUs and APUs today.  ARM processor designers are well aware of the power and efficiency benefits of utilizing all of the available transistors and processing power correctly and the emphasis on an HSA-style system design makes a lot of sense moving forward.  

My main question for the HSA Foundation is its goals: obviously they want to promote the simplistic approach for programmers, but what does that actually translate to on the hardware side?  It is possible that both x86 and ARM-based ISAs can continue to exist with libraries and compilers built to correctly handle applications for each architecture, but that would seem to me to be against the goals of such a partnership of technology leaders.

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In a meeting with AMD personnel, the most powerful and inspiring idea from the HSA Foundation is summed up with this:

"This is bigger than AMD.  This is bigger than the PC ecosystem."

The end game is to make sure that all software developers can EASILY take advantage of both traditional and parallel processing cores without ever having to know what is going on under the hood.  AMD and the other HSA Foundation members continue to tell us that this optimization can be completely ISA-agnostic – though the technical blockages for that to take place are severe. 

AMD will benefit from the success of the HSA Foundation by finally getting more partners involved in promoting the idea of heterogeneous computing, and powerful ones at that.  ARM is the biggest player in the low power processor market responsible for the Cortex and Mali architectures found in the vast majority of mobile processors.  As those partners trumpet the same cause as AMD, more software will be developed to take advantage of parallel computing and AMD believes their GPU architecture gives them a definite performance advantage once that takes hold.  

What I find most interesting is the unknown – how will this affect the roadmaps for all the hardware companies involved?  Are we going to see the AMD APU roadmap shift to an ARM-IP system?  Will we see companies like Texas Instruments fully integrate the OMAP and Power VR cores into a single memory space (or ARM with Cortex and Mali)?  Will we eventually see NVIDIA jump onboard and lend their weight towards true heterogenous computing?

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We have much more the learn about the HSA Foundation and its direction for the industry but we can easily say that this is probably the most important processor company collaboration announcement in many years – and it does so without the 800 pound gorilla that is Intel in attendance.  By going after the ARM-based markets where Intel is already struggling to compete in, AMD can hope to create a foothold with technological and partnership advantages and return to a seat of prominence.  This harkens back to the late 1990s when AMD famously put together the "virtual gorilla" with many partners to take on Intel.

Check out the full press release after the break!

Source: HSA Foundation

AFDS 2012: AMD "Kaveri" APU to offer 1 TFLOPS Compute Performance

Subject: Graphics Cards, Processors | June 12, 2012 - 12:18 PM |
Tagged: Kaveri, APU, amd, AFDS

During the opening keynote at the AMD Fusion Developer Summit 2012, AMD's Dr. Lisa Su revealed a slide with performance of the upcoming 3rd genreation Kaveri APU.

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While Trinity is currently rated at 726 GFLOPS, the Kaveri APU due late in 2012 or early 2013, will have at least 1 TFLOPS of total compute performance.  That is a 37% boost over the previous generation. 

If you want more information, check out our keynote live blog!!

Source: PC Perspective

AFDS 2012: AMD Wireless Display to compete against Intel WiDi with open standards

Subject: General Tech, Processors, Displays | June 10, 2012 - 06:45 PM |
Tagged: widi, Intel, awd, amd wireless display, amd, AFDS

While perusing through the listings and descriptions of sessions and presentations for the upcoming AMD Fusion Developer Summit, I came across an interesting one that surprised me.  Tomorrow, June 11th, at 5:15pm PST, you can stop by the Grand Hyatt in Bellevue to learn about the upcoming AMD Wireless Display technology.

AWD (AMD Wireless Display) is a multiple-platform application family to enable wireless display technologies much in the same way that Intel has been pushing with WiDi.  While Intel's take on it requires very specific Intel wireless controllers and is only recently, with the release of Ivy Bridge, getting the full-steam push from Intel, AMD's take on it is quite different.

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Intel introduced WiDi in 2010

According to the brief on this AFDS session, AMD wants to create an API and SDKs for application developers to integrate AWD into software and to leverage the WiFi Alliance for an open-standards compliant front-end.  Using AMD APUs, the goal is provide lower latency for encoded video and audio while still using the required MPEG2TS wrapper.  We are also likely to learn that AMD hopes to make AWD open to a wider array of wireless devices.

AMD often takes this "open" approach to new technologies with mixed results - CUDA has been in place for many years while the adoption of OpenCL is only starting to take hold and 3D Vision still is the standard for 3D gaming on the PC.  

After having quite a few chances to use Intel's Wireless Display (WiDi) technology myself I can definitely say that the wireless approach is the one I am most excited with and that has the most potential to revolutionize the way we work with displays and computing devices.  I am eager to see what partners AMD has been working with and what demonstrations they will have for AWD next week.

Source: AMD Fusion Developer Summit

Comprehensive Ivy Bridge testing on Ubuntu 12.04 LTS

Subject: Processors | June 8, 2012 - 03:51 PM |
Tagged: ubuntu, linux, Intel, Ivy Bridge, compiler, virtualization

Phoronix have been very busy lately, getting their heads around the functionality of Ivy Bridge on Linux and as these processor are much more compatible than their predecessors it has resulted in a lot of testing.  The majority of the testing focused on the performance of GCC, LLVM/Clang, DragonEgg, PathScale EKOPath, and Open64 on an i7-3770K using a wide variety of programs and benchmarks.  Their initial findings favoured GCC over all other compilers as in general it took top spot, with LLVM having issues with some of their tests.  They then started to play around with the instruction sets the processor was allowed to use, by disabling some of the new features they could emulate how the Ivy Bridge processor would perform if it was from a previous generation of chips, good to judge the improvement of raw processing power.  They finished up by testing its virtualization performance, with BareMetal, the Kernel-based Virtual Machine virtualization and Oracle VM VirtualBox.  You can see how they compared right here.

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"From an Intel Core i7 3770K "Ivy Bridge" system here is an 11-way compiler comparison to look at the performance of these popular code compilers on the latest-generation Intel hardware. Among the compilers being compared on Intel's Ivy Bridge platform are multiple releases of GCC, LLVM/Clang, DragonEgg, PathScale EKOPath, and Open64."

Here are some more Processor articles from around the web:

Processors

 

Source:

AMD Fusion Developer Summit 2012 - What to expect

Subject: General Tech, Processors, Shows and Expos | June 7, 2012 - 06:49 PM |
Tagged: hsa, fusion, amd, AFDS

One of the best show experiences I had last year was a surprise to me - AMD's first annual Fusion Developer Summit (AFDS) was hosted in the Seattle / Bellevue area.  I say that it was a surprise only because the inaugural year for vendor-specific shows like this tend to be pretty bland and lack interesting information, but that wasn't the case in 2011.  We saw ARM get on stage with AMD to talk about the idea of "dark silicon" and how to prevent it, we saw the first AMD Trinity notebook and even got details of the Tahiti GPU architecture well ahead of release.  

We expect even better things in 2012.

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While I don't know exactly what surprises will be on display this year I am looking forward to seeing the improvement from software developers after having another 12 months to work on APU-accelerated applications.  HSA (heterogeneous system architecture) has been getting a lot of buzz from AMD and the industry as we push towards a combined memory address space and the ultimate acceleration of programs across both serialized and parallel processors on the same die.

If you are in the Seattle / Bellevue area and you have the ability to attend AFDS, I would highly encourage you to do so.  You'll have access to:

  • Keynotes
  • Never before seen demos
  • Technical tracks and sessions to learn about HSA and programming for it

If you can't make it though, you should definitely follow the whole event right here at PC Perspective - the easiest way is to keep track of our AFDS tag to make sure you don't miss any of the potentially industry shifting news! 

You can also expect us to have a live blog from the event as well!

Source: PC Perspective

AMD Releases Brazos 2.0, dual-core Bobcat for low power platforms

Subject: Processors | June 6, 2012 - 05:08 PM |
Tagged: Zacate, Hudson-M3L, FCH, E2-1800, E2-1200, computex, brazos 2.0, brazos, Bobcat, amd

 Today AMD is officially releasing their Brazos 2.0 parts. This is a case of good news/bad news for the company. The good news is that they have an updated product that is based on their very successful Brazos 1.0 platform and that particular part has sold over 30 million units and is included in some 160 designs. The bad news is that AMD did not improve the product dramatically over what we previously had.

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While Brazos will not beat these Intel offerings in pure performance, they do match up nicely in terms of price and battery life.

It is well known that AMD cancelled their original Bobcat 2.0 28 nm parts last fall (Krishna and Wichita), and instead worked on improving the fabrication of the current Brazos APUs. Little is known as to why those original 28 nm parts were cancelled, but perhaps the overriding reason is that there simply would not be enough 28 nm production through the first three quarters of 2012 to enable AMD to adequately meet demand on these parts (all the while sacrificing higher margin GPU wafer orders on the 28 nm node). We also must consider that AMD could have been counting on GLOBALFOUNDRIES to have their flavor of 28 nm HKMG process up and running, which of course at this time it is not.

These new Brazos 2.0 chips are still manufactured on TSMC’s 40 nm process, but that particular process is very mature at this time. This has allowed AMD and TSMC to squeeze every last drop of performance and efficiency out of the aging 40 nm node, and in so doing has allowed AMD a bit more headroom when it comes to the Zacate APUs that Brazos 2.0 is based off of. The two new processors are the E2-1800 and the E2-1200.

The E2-1800 is a dual core Bobcat CPU featuring an APU with 80 stream units based on the older HD 5000 series of parts. AMD has renamed the GPU to the HD 7340, though it has little in common with the GCN (Graphics Core Next) based HD 7000 graphics units. AMD increased the core CPU speed from the E-450 by 50 MHz and the GPU portion by 80 MHz. This gives the E2-1800 a core clockspeed of 1.7 GHz and the graphics runs at a brisk 680 MHz. This continues to be an 18 watt TDP part and the die size is the same 75 mm squared.

Click here to read more.

Source: AMD

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