IDF Spring 2006 Day 1: New Core Architecture Overview
Intel's New Core Micro Architectgure
Intel knows that energy efficiency and performance are competing with one another in the CPU market. This is analogous to the battle that car manufacturers have where they must make compromises between making an energy efficient vehicle (Toyota Prius) or making one that is fun to drive (Dodge Viper).
Since the original Pentium processor, Intel admits that the amount of power needed for each instruction that was executed was going the wrong way, all the way through the Pentium 4, as each instruction was more and more expensive on energy. The Israel design team at Intel that was responsible for the Pentium M core found another way to do things that nearly reversed all the years of a downward trend that Intel had been in. Core Duo expanded that principle even more so and increased the overall performance of the processor with multiple cores.
In preparation for the new Intel Core Architecture, Intel has readied their new 65nm process technology that will offer up to 20% more transistor performance and will use 30% less switching power. The 45nm process is already well into the Intel pipeline as well and will be ready in 2007. It will require the same 30% decrease in switching power and 20% increase in transistor performance, but this time relative to the 65nm process.
The new core architecture that is behind the Merom and Conroe technologies has five key points according to Ratner's keynote. First we have a new, wider instruction pathway that can work on four instructions per clock. Doing more instructions in the same number clocks can easily equate to doing more in less time and with less power. Additionally, Ratner noted they are still using the same 14-stage execution pipeline as the Yonah core, so there are no expansions here.
The new instruction process also has a higher ability to fuse micro and now macro operations into a single instruction thus getting even more instructions done per clock. Similarly, one of the other main new features of Intel new core architecture is the ability to perform the entire family of SSE instructions in a single clock. Compared to before on Pentium 4 and Pentium M level processors, that had to do many of the SSE instructions in multiple clocks; this should offer a performance advantage to video and audio application that utilizes these instruction sets.
A new shared L2 cache will also help improve the efficiency and performance of the Merom and Conroe cores. Both cores on the processor have access to the same L2 cache, thus allowing the processors to easily share information between them. Even when one of the cores is completely disabled the other core has access to the entire L2 cache as no part of it is ever fully fixated to either of the cores.
Intel has added an improved pre-fetch design on the new core architecture to improve memory access and also can reorder memory commands in hardware to improve performance. A memory load that is more important to performance can now be moved in front of any other commands at the processors discretion, regardless of core logic used.
Finally, more advanced power gating is being utilized on the new core architecture that expands on what the Pentium M first introduced in the mobile market. As we already know, power gating simply allows the processor to shut down parts of the core that are not being used in order to save on power consumption dramatically. We'll have more information on all these new architecture features latest in the week as the more detailed information is released.
Page 2 - Merom and Conroe Make Their Debut