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Next Gen Graphics and Process Migration: 20 nm and Beyond

Author: Josh Walrath
Subject: Editorial
Manufacturer:

What is the Point of this Editorial?

Many people were waiting on a true, next generation GPU to be released at this time.  While the Hawaii GPU from AMD is a new (and potentially exciting) part, it is not the big jump that many were hoping for.  It looks to compete with the GTX TITAN, but it will not leapfrog that part.  It will probably end up faster, but by a couple of percentage points.  It will not be the big jump we have seen in the past such as going from a GTX 580 or HD 6970 to a GTX 680 or HD 7970.

Until 20 nm HKMG becomes available for production, we are in for a wait.  TSMC expects to be able to provide mass quantities of these parts by Q3 2014, but that is not entirely set in stone.  My gut feeling here is that TSMC will be pretty close to that timeline and we would expect to see 20 nm GPUs hitting the market in around a year from now.  The problem that we are potentially looking at could very well be heat and power constraints holding these designs back.  I do not doubt that it will be a nice jump in terms of performance from these next gen parts, but the use of 20 nm bulk will limit the potential of these products from a power consumption standpoint.

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The NVIDIA GK110, which powers the GTX Titan and GTX 780, is a huge chip which packs in over 7 billion transistors.  Expect to see this (and possibly a refreshed version) be the top end chip for a while.

If GLOBALFOUNDRIES has the ability to economically research, develop, and produce parts on 20 nm FD-SOI, they could be hitting one out of the park.  The industry is clamoring for a product that can match the power characteristics of Intel’s 22 nm process.  Intel’s Baytrail products are causing much concern for the ARM folks, though it will still be a while before Intel can ingratiate itself into many of the major handheld manufacturers who have longstanding partnerships with companies such as Qualcomm and Samsung.  3D FinFETs from TSMC are still at least 2 years away on 20 nm, not to mention sub-20 nm lines like 16 nm and 14 nm products that have been described by pure-play foundries.

Intel is also very close to production of 14 nm parts towards the end of this year.  The 14 nm process is again Tri-Gate based with bulk silicon wafers.  Intel claims that it can adequately control power and clockspeed, but I find it telling that the first products to be introduced on 14 nm are BGA only based Broadwell parts.  On the desktop there will be a Haswell refresh at 22 nm.  This indicates that 14 nm will again be a nice step up in transistor density and low speed power consumption, but for desktop and workstation applications it might not be entirely adequate.  Beyond 14 nm Intel is in fact looking at FD-SOI very carefully.  In the end, materials are king when it comes to process technology.  We have also just learned that Intel is delaying the Broadwell introduction for at least a quarter due to unacceptable defect levels on their 14 nm process with this particular product.  Even with billions in R&D and some of the most talented engineers in the industry, Intel still faces many problems with their introduction of advanced process nodes.

For the pure-play foundries they will have to rely on FinFET technology to go below 20 nm.  We will see a good mix of bulk and FD-SOI products, though we have no idea who else ST-Micro will license FD-SOI to.  The combination of FinFET/FD-SOI holds a lot of promise, but we are still at least three years away from such an implementation.

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It was all downhill for process technology after they allowed Allyn into a Fab.  He ruins everything.

The long and short of it is that we can expect longer time intervals between releases of next-generation GPU architectures as they are being constrained by the very latest process technology available.  20 nm bulk will be one year from now, 20 nm FD-SOI is at least 1.5 years away, and any process node below that appropriate for GPUs will be another 3 years.  AMD and NVIDIA will have to do a lot of work to implement next generation features without breaking transistor budgets.  They will have to do more with less, essentially.  Either that or we will just have to deal with a much slower introduction of next generation parts.  Marketing and product segmentation will rear their ugly heads, and we will see a very slow reduction in prices from when a product is introduced.  We have been spoiled for the past 18 years, but it seems like the good times are over and a whole lot of work is ahead of both designers and foundries.

We still have many years ahead of us for product advancement, and that will continue until we start seeing the 7 nm to 5 nm process nodes.  After that, we are in for some rough times.  Quantum physics will start to derail silicon based chips and we will have to move to more exotic materials to keep pace.  This is all assuming that EUV will actually work as intended.  If that does not happen, then we will have to look at other potential lithography measures such as x-ray.  There are many, many challenges ahead of the process technology people, and until some of these basic problems are solved we will likely never again see the rapid march of technology that we have experienced since the birth of the silicon transistor some 50 years ago.

October 22, 2013 | 06:12 PM - Posted by snook

thanks Josh. Lets hope there is that one guy who says "how about trying this?", and he changes everything.

October 22, 2013 | 09:50 PM - Posted by Josh Walrath

Make no mistake, there is a lot of research in a LOT of different areas to overcome the issues that the industry is running into.  The challenges have always been there (breaking the 1 micron barrier was seemingly huge), but now the challenges are just bigger, more complex, and more expensive.

October 25, 2013 | 11:56 AM - Posted by Anonymous (not verified)

Or maybe one of the foundrys will have a happy accident Bob Ross style.

They'll come in one monring to find their equipment had slipped around a new nm during the night and everything is a little out of whack. They're about to toss out the batch when someone grabs a wafer for the fun of it and runs a test and BAM! breakthrough!

Guy can dream, can't he.

October 22, 2013 | 06:26 PM - Posted by Evo01

Thanks Josh. Fantastic article.

October 22, 2013 | 07:46 PM - Posted by Fishbait

Very awesome and informative article Josh. What implications could this have with Moore’s law? Does this effectively stop it before the theoretical quantum limit in 2036? These will be an interesting few years for pure-play foundries and their clients indeed.

October 22, 2013 | 09:52 PM - Posted by Josh Walrath

Well, things will be necessarily slowing down.  There simply are hurdles that need lots of time and lots of money to solve.  10 nm shouldn't be that bad, 7 nm is hitting some interesting limits, and sub 7 nm is going to be really rough.  Litho, materials, and electrical characterisitcs at that size will be sorta crazy.

October 22, 2013 | 08:26 PM - Posted by Anonymous (not verified)

Just to add a few points to this excellent article:

- The 14nm/16nm nodes for GloFo and TSMC, respectively, are going to be utilizing a 20nm back-end-of-line. This means that while density won't increase, they'll improve power characteristics (these are the two FinFET nodes).

- The time-to-market for the above two nodes from both foundries should be more painless than if they were to attempt a shrink + FinFETs. As a result, if I were to guess I'd say we see the 14nm/16nm nodes a bit earlier than some had anticipated. Early tape-outs for 14nm and 20nm have been close together so that definitely adds some credence to that line of thought. Though not certainty ;P

- These node names (eg., 14nm) don't actually accurately describe the half-pitch. Unless I'm recalling incorrectly, the current tools would only allow something like 18nm(?). Intel's current 22nm FinFETs has been described in papers as 26nm. Whether that's true or not, I have no idea, but the point is that the half-pitch is only a single detail in a long list of attributes that defines a new "node." The takeaway is that you shouldn't get too caught up in the XXnm numbers and remember that it's the power, leakage, density, and performance of the node that actually matters.

October 22, 2013 | 08:43 PM - Posted by Josh Walrath

Thanks for the comments.

About the node names... Intel's 22 nm describes the smallest feature, but you are correct in that a certain other feature (I think it has to do with SRAM) is 26 nm.  There was some thought that AMD with GF's 28 nm would be able to get fairly close to the transistor density of Intel's 22 nm in certain aspects due to this size variance.

October 22, 2013 | 09:29 PM - Posted by Krewell (not verified)

Nice summary Josh. As the person above noted above, the node numbers are not strictly related to feature size (e.g. TSMC 16nm is FinFET transistors on 20nm backend).

Nvidia likes to talk about how GPUs have better than Moore's Law scaling, but with die sizes already at 550mm2 (GK110), that will not be true going forward - die sizes are already close to the limits of fab reticles (~600mm2).

I just had this same conversation with AMD's Raja Kudari. Raja's response is that it will take new architectures to improve performance, not just process shrinks and die area growth. It's going to take improvements in architecture efficiency and effectiveness. It also means that the GPU designers need to work closer with game engine developers to find efficiency improvements - Mantle is one example.

October 22, 2013 | 09:45 PM - Posted by Josh Walrath

If you have some spare minutes, you should read that old article I linked.  Some interesting stuff there (considering it was written in 2004 and issues at 130 nm were just being solved).

Thanks for reading!  The next few years are going to be very interesting considering the challenges ahead!

October 23, 2013 | 01:32 AM - Posted by Fiberton (not verified)

Reason I found it interesting that last year AMD replaced CPU architects that were the creators of the Athlon. We all really need AMD to do well to drive pricing down for everyone and to also push technology forward.

October 23, 2013 | 02:03 AM - Posted by Fiberton (not verified)

I wish I could edit :) They replaced the bulldozer architect. They have hired people who worked on the Athlon projects. 1 am sorry :).

October 23, 2013 | 01:09 PM - Posted by Josh Walrath

Yeah, some of the old guys came back.  Jim Keller is the big name.  Raja Koduri on the GPU side is back.  There is a lot of uplift in what they are trying to do, and I think overall they are heading in the right direction.  I like Dirk Meyer, but while he was a great CPU architect, he almost missed the major mobile transition that his product stack would not be able to address.

October 22, 2013 | 09:32 PM - Posted by Whayne (not verified)

Wonderful and informative post Josh. As a theoretical physicist with some background in solid state physics I've been aware of a few of the issues facing the industry especially the lithography. I cannot even begin to imagine how hard it's going to be to get 7-5nm process nodes operational. I expect quantum effects to come in earlier maybe even 10nm will be very tough. Quantum tunnelling will no doubt be a huge issue when line traces are so small.

Interesting times ahead. It looks like either an R9 290x or a GTX 780 Ti will be my friend until well into 2015, but that's okay, as they are still going to be pretty darn good cards.

October 22, 2013 | 09:42 PM - Posted by Josh Walrath

I find it interesting that pretty much the entire industry is heavily invested in EUV... and from what I understand, the risk there is still very high that it will even work out.

October 24, 2013 | 02:30 PM - Posted by Frenchy2k1 (not verified)

The industry has been working on EUV for over 10 years already and still seems quite far from its target (which has been moving during that time too).

Those are interesting times indeed at the process level.

The question you have not breached is about the economics of it. We have been seeing a lot of consolidation in the semiconductor for the past ten years and it is accelerating. Each process node cost exponentially more than the last one and THIS is the reason for pure play foundries: few companies can afford their own fabs anymore. Intel is of course the exception, but even they are starting to open their fabs to other companies (which nobody would expect just a few years ago). That means that even intel has too much capacity and cannot fill its fabs anymore.

Semiconductor is so far the pinnacle of human ingenuity, taking so much efforts from so many people to keep on track and follow Moore's Law. All those people are hard at work on EUV and backup plans (multiple patterning, they are doing dual, but 3 or 4 are definitely possible, 3D transistors are also coming, first in Flash at Samsung). We have not yet seen the end of semiconductor growth.

October 22, 2013 | 10:12 PM - Posted by Anonymous (not verified)

Looks like someone got influenced by their trip to Montreal.

October 22, 2013 | 10:17 PM - Posted by Josh Walrath

Heh, I didn't go to Montreal with Ryan and Ken.  Oddly enough, I started researching and writing this before that event.  I was sorta cranky when Carmack started talking about this subject... day late and a dollar short for me (or rather many millions of dollars short).

October 23, 2013 | 01:38 AM - Posted by Fiberton (not verified)

Your article really reminds of the past seeing the names of all the cards and players in the market. There was so much more excitement back then. Thanks for the read 0/

October 22, 2013 | 11:18 PM - Posted by Jerald Tapalla (not verified)

This is the first time I just sit and read a long article with my focus just on it. Very nice article, very informative especially for me who is new to this kind of stuff. Thanks for this.

October 22, 2013 | 11:38 PM - Posted by Josh Walrath

Thanks for reading the entire thing!  Ryan will thank you as well!

October 22, 2013 | 11:57 PM - Posted by Onehourleft

Great writing Josh. Also it was nice to visit your archives for the first time. I enjoyed both articles.

October 23, 2013 | 01:29 AM - Posted by MeezyATL (not verified)

Some great articles from the PC Per staff this week. Keep up the good work.

October 23, 2013 | 05:06 AM - Posted by thinkbiggar (not verified)

Can you run that thing in SLI? Also did it cause you to loose all your hair?
I bet the prices stayed the same but not with inflation. Don't tell marketing people about inflation. Once they learn about it we are all screwed.

October 23, 2013 | 01:11 PM - Posted by Josh Walrath

I lost my hair because I got married and had kids.

October 23, 2013 | 07:01 AM - Posted by WantT100 (not verified)

This is a stunning article, this is why I visit Pcper every day. Ryan give the man a bonus!

This article is up there with Scott's "The Windows You Love is Gone" stunner a year ago.
http://www.pcper.com/reviews/Editorial/Windows-You-Love-Gone

October 23, 2013 | 08:13 AM - Posted by Anonymous (not verified)

These kind of delays are to be expected. The smaller you go, the indiviual effects become that much ore pronounced. Instead of treating the design as a whole or in smaller but relatively large units, more research needs to be done in examining each and every change occuring within the system. Very time consuming and expensive. I will not be surprised if there are further delays. The break-neck speed of development had to come to an end some time.

Not disappointed about delays but very much expected. Can´t keep throwing money and expect it to pay dividends immediatly. My 2 cents.

October 23, 2013 | 12:46 PM - Posted by Josh Walrath

Yup, you are likely correct.  What we often don't hear about is how closely the fab engineers work with the designers.  The amount of back and forth work and information they do is pretty staggering, especially with these next generation nodes.  This simply isn't a "we are finished with the design, send it to the Fab guys and they can figure out the rest!" situation anymore.

We are also seeing the pure-play guys working to amortize their investments in current process nodes... because the next gen stuff is so expensive.  Gotta pay those bills.  They only hope that Intel will slow down, cause those guys don't clear $3 billion a quarter like Intel does.

October 23, 2013 | 10:25 AM - Posted by blitzio

Amazing article Josh, thank you for an informative read. I feel thoroughly educated.

October 23, 2013 | 10:29 AM - Posted by Max KreFey

Great article Josh! Thank you from cold mother Russia! :D

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