Next Gen Graphics and Process Migration: 20 nm and Beyond
20 nm and Below
Getting to 20 nm for these foundries is a challenge. The first area is that of lithography. The industry is not at the point where EUV (Extreme UV) is effective or affordable- or even workable for that matter. To achieve the geometries required the foundries have to use immersion litho, multiple-patterning, and other optical techniques to effectively complete the litho stage. This is not even delving into the materials needed. Currently plans are that these will be bulk silicon wafers, but they will be using second generation HKMG, third generation SiGe strain technologies, and a gate-last approach. The current 28 nm HKMG process from TSMC employs a less complex gate first approach that is more cost effective. At 20 nm, there really is no choice but to force 3rd parties to adopt gate last to get the best results.
Some two years ago GLOBALFOUNDRIES showed off their test 28 nm SRAM wafers. Nobody expected them to be as delayed as they ended up being.
TSMC and others are busy developing their own technology akin to Tri-Gates. These are called 3D Fin-FETs. The basic design and physics behind these structures are essentially the same, but Intel trademarked theirs first. The problem here is that we are still at least two years away from an effective implementation of FinFETs on any node from any pure-play foundry. So the GPU guys are looking at a new process node that will effectively shrink the transistors, but may not have the electrical characteristics they were hoping for. TSMC is not planning on opening up their 20 nm HKMG planar based lines until Q1/Q2 2014 with product being delivered in a Q3 timeframe. TSMC is ahead of the bunch so far with actually implementing a 20 nm line.
GLOBALFOUNDRIES is also developing advanced process nodes, but so far things have been disappointing for the company. When they first came on the scene some years back there was a lot of hope that they could move past TSMC in terms of implementing advanced process technologies since they had the impetus of being ahead in the days when AMD owned the fabs. That impetus soon went away once the price of implementing these advanced technologies did not mesh with the economics of being a pure-play foundry. While TSMC had opened their 28 nm HKMG nearly two years ago, it was less than a year ago that GF opened their 28 nm line to customers. So far the designs from GF’s 28 nm have essentially been smaller SOCs from players like MediaTek and Rockchip. AMD’s Kaveri APU has been delayed from what looks to be fabrication issues rather than design issues. We do not expect to see Kaveri in mass quantities until Q1 2014. GF has been behind the times when it comes to process technology, but some interesting things have come up that could change the landscape.
SOI Strikes Again
Who all thought that SOI was dead after AMD decided to stop using it after moving away from GF’s 32 nm PD-SOI process? Well, more than a few, but the truth is SOI is a very handy technology that is used in many other products, one of which is high speed RF switching applications. AMD has been utilizing PD-SOI for many generations of parts. Partially-Depleted is an older and well understood substrate that has done very well for AMD. Unfortunately for AMD, 32 nm was really the last gasp for PD-SOI. Going below that size, the electrical characteristics of PD-SOI are not that much better than bulk silicon. Though there is a positive difference, it is not enough to justify the 10% to 15% increase in wafer costs and slightly more complex manufacturing process.
The future site of FD-SOI integration? Fab 8 is a sprawling complex that could be the new epicenter of advanced materials research utilzing SOI.
All is not lost for SOI. FD-SOI (fully depleted) looks to be a very interesting and cost effective strategy for going below 28 nm. FD-SOI does cost more per wafer, but most of the processing equipment is the same as for bulk silicon. There does need to be special handling and usage of materials, but it is not nearly as complex as implementing FinFETs. FD-SOI will utilize planar transistors, making manufacturing much more simple than that required for FinFETS.
The problem with FD-SOI manufacturing is that so far only one company has done it. ST-Micro owns and operates a small Fab in France that can produce, at max, around 500 wafer starts per week. Most of the mega-Fabs around the world can produce around 5000 to 12,000 wafer starts per week. This Fab obviously cannot provide enough manufacturing space except for small clients with minimal needs. ST-Micro has licensed out the technology to GLOBALFOUNDRIES, but the next issue is that so far it is aimed at only two nodes; 28 nm and the distant 14 nm. We do not know if GF has plans for 20 nm, but looking at the global marketplace and the potential demand it seems that 20 nm FD-SOI would be a very good target to aim at.
FD-SOI seems like it answers most of the issues that crop up with the 22/20 nm node. It does not require massive design rule changes, it can re-use a lot of bulk silicon manufacturing technology, and it runs perfectly fine with planar transistors at 22/20 nm. In a gate-last configuration, FD-SOI with planar transistors actually looks like it outperforms and scales significantly better than Intel’s 22 nm Tri-Gate process. A theoretical 20 nm FD-SOI process would have smaller features and be able to scale with clockspeed without as steep a power curve than what we see currently with Intel’s 22 nm Tri-Gate. In terms of lower power operation, it appears as though FD-SOI is no better or worse than what Intel offers.
The machinery is prepped and ready for GLOBALFOUNDRIES, but until we see how they do with mass production of Kaveri, we are unsure where they really sit.
Sounds perfect, right? The problem is of course money and man-hours. FD-SOI wafers are not being mass produced at this time, though production can be ramped up fairly quickly. GF has yet to implement 28 nm FD-SOI at any of their fabs and the timeline for manufacturing products on this process has yet to be determined (or at least released to the general public). Also, there is no public roadmap for a 20 nm FD-SOI process to be offered from anyone.
GF has only now started mass production of the latest generation of AMD APUs based on 28 nm. The previous Kabini APUs were all produced by TSMC on their 28 nm process. GF’s work on 20 nm has been confined to their test labs and very little is known about its characteristics. Perhaps they are going for the jugular and are preparing a 20 nm FD-SOI, but so far their track record for hitting their process milestones has been lacking. GF has increased their marketshare and are more competitive with TSMC, but so far they have not been able to compete adequately with what TSMC offers (plus their revenue is 1/5 that of TSMC). Working with ST-Micro to implement 28 nm FD-SOI is a benefit for the company as there are customers who are interested in that particular node. The performance and power results on ARM processors on 28 nm FD-SOI are outstanding, especially considering the relatively small cost increase to utilize FD-SOI wafers.
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