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Next Gen Graphics and Process Migration: 20 nm and Beyond

Author: Josh Walrath
Subject: Editorial
Manufacturer:

20 nm and Below

Getting to 20 nm for these foundries is a challenge.  The first area is that of lithography.  The industry is not at the point where EUV (Extreme UV) is effective or affordable- or even workable for that matter.  To achieve the geometries required the foundries have to use immersion litho, multiple-patterning, and other optical techniques to effectively complete the litho stage.  This is not even delving into the materials needed.  Currently plans are that these will be bulk silicon wafers, but they will be using second generation HKMG, third generation SiGe strain technologies, and a gate-last approach.  The current 28 nm HKMG process from TSMC employs a less complex gate first approach that is more cost effective.  At 20 nm, there really is no choice but to force 3rd parties to adopt gate last to get the best results.

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Some two years ago GLOBALFOUNDRIES showed off their test 28 nm SRAM wafers.  Nobody expected them to be as delayed as they ended up being.

TSMC and others are busy developing their own technology akin to Tri-Gates.  These are called 3D Fin-FETs.  The basic design and physics behind these structures are essentially the same, but Intel trademarked theirs first.  The problem here is that we are still at least two years away from an effective implementation of FinFETs on any node from any pure-play foundry.  So the GPU guys are looking at a new process node that will effectively shrink the transistors, but may not have the electrical characteristics they were hoping for.  TSMC is not planning on opening up their 20 nm HKMG planar based lines until Q1/Q2 2014 with product being delivered in a Q3 timeframe.  TSMC is ahead of the bunch so far with actually implementing a 20 nm line.

GLOBALFOUNDRIES is also developing advanced process nodes, but so far things have been disappointing for the company.  When they first came on the scene some years back there was a lot of hope that they could move past TSMC in terms of implementing advanced process technologies since they had the impetus of being ahead in the days when AMD owned the fabs.  That impetus soon went away once the price of implementing these advanced technologies did not mesh with the economics of being a pure-play foundry.  While TSMC had opened their 28 nm HKMG nearly two years ago, it was less than a year ago that GF opened their 28 nm line to customers.  So far the designs from GF’s 28 nm have essentially been smaller SOCs from players like MediaTek and Rockchip.  AMD’s Kaveri APU has been delayed from what looks to be fabrication issues rather than design issues.  We do not expect to see Kaveri in mass quantities until Q1 2014.  GF has been behind the times when it comes to process technology, but some interesting things have come up that could change the landscape.

 

SOI Strikes Again

Who all thought that SOI was dead after AMD decided to stop using it after moving away from GF’s 32 nm PD-SOI process?  Well, more than a few, but the truth is SOI is a very handy technology that is used in many other products, one of which is high speed RF switching applications.  AMD has been utilizing PD-SOI for many generations of parts.  Partially-Depleted is an older and well understood substrate that has done very well for AMD.  Unfortunately for AMD, 32 nm was really the last gasp for PD-SOI.  Going below that size, the electrical characteristics of PD-SOI are not that much better than bulk silicon.  Though there is a positive difference, it is not enough to justify the 10% to 15% increase in wafer costs and slightly more complex manufacturing process. 

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The future site of FD-SOI integration?  Fab 8 is a sprawling complex that could be the new epicenter of advanced materials research utilzing SOI.

All is not lost for SOI.  FD-SOI (fully depleted) looks to be a very interesting and cost effective strategy for going below 28 nm.  FD-SOI does cost more per wafer, but most of the processing equipment is the same as for bulk silicon.  There does need to be special handling and usage of materials, but it is not nearly as complex as implementing FinFETs.  FD-SOI will utilize planar transistors, making manufacturing much more simple than that required for FinFETS.

The problem with FD-SOI manufacturing is that so far only one company has done it.  ST-Micro owns and operates a small Fab in France that can produce, at max, around 500 wafer starts per week.  Most of the mega-Fabs around the world can produce around 5000 to 12,000 wafer starts per week.  This Fab obviously cannot provide enough manufacturing space except for small clients with minimal needs.  ST-Micro has licensed out the technology to GLOBALFOUNDRIES, but the next issue is that so far it is aimed at only two nodes; 28 nm and the distant 14 nm.  We do not know if GF has plans for 20 nm, but looking at the global marketplace and the potential demand it seems that 20 nm FD-SOI would be a very good target to aim at.

FD-SOI seems like it answers most of the issues that crop up with the 22/20 nm node.  It does not require massive design rule changes, it can re-use a lot of bulk silicon manufacturing technology, and it runs perfectly fine with planar transistors at 22/20 nm.  In a gate-last configuration, FD-SOI with planar transistors actually looks like it outperforms and scales significantly better than Intel’s 22 nm Tri-Gate process.  A theoretical 20 nm FD-SOI process would have smaller features and be able to scale with clockspeed without as steep a power curve than what we see currently with Intel’s 22 nm Tri-Gate.  In terms of lower power operation, it appears as though FD-SOI is no better or worse than what Intel offers.

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The machinery is prepped and ready for GLOBALFOUNDRIES, but until we see how they do with mass production of Kaveri, we are unsure where they really sit.

Sounds perfect, right?  The problem is of course money and man-hours.  FD-SOI wafers are not being mass produced at this time, though production can be ramped up fairly quickly.  GF has yet to implement 28 nm FD-SOI at any of their fabs and the timeline for manufacturing products on this process has yet to be determined (or at least released to the general public).  Also, there is no public roadmap for a 20 nm FD-SOI process to be offered from anyone.

GF has only now started mass production of the latest generation of AMD APUs based on 28 nm.  The previous Kabini APUs were all produced by TSMC on their 28 nm process.  GF’s work on 20 nm has been confined to their test labs and very little is known about its characteristics.  Perhaps they are going for the jugular and are preparing a 20 nm FD-SOI, but so far their track record for hitting their process milestones has been lacking.  GF has increased their marketshare and are more competitive with TSMC, but so far they have not been able to compete adequately with what TSMC offers (plus their revenue is 1/5 that of TSMC).  Working with ST-Micro to implement 28 nm FD-SOI is a benefit for the company as there are customers who are interested in that particular node.  The performance and power results on ARM processors on 28 nm FD-SOI are outstanding, especially considering the relatively small cost increase to utilize FD-SOI wafers.

October 22, 2013 | 06:12 PM - Posted by snook

thanks Josh. Lets hope there is that one guy who says "how about trying this?", and he changes everything.

October 22, 2013 | 09:50 PM - Posted by Josh Walrath

Make no mistake, there is a lot of research in a LOT of different areas to overcome the issues that the industry is running into.  The challenges have always been there (breaking the 1 micron barrier was seemingly huge), but now the challenges are just bigger, more complex, and more expensive.

October 25, 2013 | 11:56 AM - Posted by Anonymous (not verified)

Or maybe one of the foundrys will have a happy accident Bob Ross style.

They'll come in one monring to find their equipment had slipped around a new nm during the night and everything is a little out of whack. They're about to toss out the batch when someone grabs a wafer for the fun of it and runs a test and BAM! breakthrough!

Guy can dream, can't he.

October 22, 2013 | 06:26 PM - Posted by Evo01

Thanks Josh. Fantastic article.

October 22, 2013 | 07:46 PM - Posted by Fishbait

Very awesome and informative article Josh. What implications could this have with Moore’s law? Does this effectively stop it before the theoretical quantum limit in 2036? These will be an interesting few years for pure-play foundries and their clients indeed.

October 22, 2013 | 09:52 PM - Posted by Josh Walrath

Well, things will be necessarily slowing down.  There simply are hurdles that need lots of time and lots of money to solve.  10 nm shouldn't be that bad, 7 nm is hitting some interesting limits, and sub 7 nm is going to be really rough.  Litho, materials, and electrical characterisitcs at that size will be sorta crazy.

October 22, 2013 | 08:26 PM - Posted by Anonymous (not verified)

Just to add a few points to this excellent article:

- The 14nm/16nm nodes for GloFo and TSMC, respectively, are going to be utilizing a 20nm back-end-of-line. This means that while density won't increase, they'll improve power characteristics (these are the two FinFET nodes).

- The time-to-market for the above two nodes from both foundries should be more painless than if they were to attempt a shrink + FinFETs. As a result, if I were to guess I'd say we see the 14nm/16nm nodes a bit earlier than some had anticipated. Early tape-outs for 14nm and 20nm have been close together so that definitely adds some credence to that line of thought. Though not certainty ;P

- These node names (eg., 14nm) don't actually accurately describe the half-pitch. Unless I'm recalling incorrectly, the current tools would only allow something like 18nm(?). Intel's current 22nm FinFETs has been described in papers as 26nm. Whether that's true or not, I have no idea, but the point is that the half-pitch is only a single detail in a long list of attributes that defines a new "node." The takeaway is that you shouldn't get too caught up in the XXnm numbers and remember that it's the power, leakage, density, and performance of the node that actually matters.

October 22, 2013 | 08:43 PM - Posted by Josh Walrath

Thanks for the comments.

About the node names... Intel's 22 nm describes the smallest feature, but you are correct in that a certain other feature (I think it has to do with SRAM) is 26 nm.  There was some thought that AMD with GF's 28 nm would be able to get fairly close to the transistor density of Intel's 22 nm in certain aspects due to this size variance.

October 22, 2013 | 09:29 PM - Posted by Krewell (not verified)

Nice summary Josh. As the person above noted above, the node numbers are not strictly related to feature size (e.g. TSMC 16nm is FinFET transistors on 20nm backend).

Nvidia likes to talk about how GPUs have better than Moore's Law scaling, but with die sizes already at 550mm2 (GK110), that will not be true going forward - die sizes are already close to the limits of fab reticles (~600mm2).

I just had this same conversation with AMD's Raja Kudari. Raja's response is that it will take new architectures to improve performance, not just process shrinks and die area growth. It's going to take improvements in architecture efficiency and effectiveness. It also means that the GPU designers need to work closer with game engine developers to find efficiency improvements - Mantle is one example.

October 22, 2013 | 09:45 PM - Posted by Josh Walrath

If you have some spare minutes, you should read that old article I linked.  Some interesting stuff there (considering it was written in 2004 and issues at 130 nm were just being solved).

Thanks for reading!  The next few years are going to be very interesting considering the challenges ahead!

October 23, 2013 | 01:32 AM - Posted by Fiberton (not verified)

Reason I found it interesting that last year AMD replaced CPU architects that were the creators of the Athlon. We all really need AMD to do well to drive pricing down for everyone and to also push technology forward.

October 23, 2013 | 02:03 AM - Posted by Fiberton (not verified)

I wish I could edit :) They replaced the bulldozer architect. They have hired people who worked on the Athlon projects. 1 am sorry :).

October 23, 2013 | 01:09 PM - Posted by Josh Walrath

Yeah, some of the old guys came back.  Jim Keller is the big name.  Raja Koduri on the GPU side is back.  There is a lot of uplift in what they are trying to do, and I think overall they are heading in the right direction.  I like Dirk Meyer, but while he was a great CPU architect, he almost missed the major mobile transition that his product stack would not be able to address.

October 22, 2013 | 09:32 PM - Posted by Whayne (not verified)

Wonderful and informative post Josh. As a theoretical physicist with some background in solid state physics I've been aware of a few of the issues facing the industry especially the lithography. I cannot even begin to imagine how hard it's going to be to get 7-5nm process nodes operational. I expect quantum effects to come in earlier maybe even 10nm will be very tough. Quantum tunnelling will no doubt be a huge issue when line traces are so small.

Interesting times ahead. It looks like either an R9 290x or a GTX 780 Ti will be my friend until well into 2015, but that's okay, as they are still going to be pretty darn good cards.

October 22, 2013 | 09:42 PM - Posted by Josh Walrath

I find it interesting that pretty much the entire industry is heavily invested in EUV... and from what I understand, the risk there is still very high that it will even work out.

October 24, 2013 | 02:30 PM - Posted by Frenchy2k1 (not verified)

The industry has been working on EUV for over 10 years already and still seems quite far from its target (which has been moving during that time too).

Those are interesting times indeed at the process level.

The question you have not breached is about the economics of it. We have been seeing a lot of consolidation in the semiconductor for the past ten years and it is accelerating. Each process node cost exponentially more than the last one and THIS is the reason for pure play foundries: few companies can afford their own fabs anymore. Intel is of course the exception, but even they are starting to open their fabs to other companies (which nobody would expect just a few years ago). That means that even intel has too much capacity and cannot fill its fabs anymore.

Semiconductor is so far the pinnacle of human ingenuity, taking so much efforts from so many people to keep on track and follow Moore's Law. All those people are hard at work on EUV and backup plans (multiple patterning, they are doing dual, but 3 or 4 are definitely possible, 3D transistors are also coming, first in Flash at Samsung). We have not yet seen the end of semiconductor growth.

October 22, 2013 | 10:12 PM - Posted by Anonymous (not verified)

Looks like someone got influenced by their trip to Montreal.

October 22, 2013 | 10:17 PM - Posted by Josh Walrath

Heh, I didn't go to Montreal with Ryan and Ken.  Oddly enough, I started researching and writing this before that event.  I was sorta cranky when Carmack started talking about this subject... day late and a dollar short for me (or rather many millions of dollars short).

October 23, 2013 | 01:38 AM - Posted by Fiberton (not verified)

Your article really reminds of the past seeing the names of all the cards and players in the market. There was so much more excitement back then. Thanks for the read 0/

October 22, 2013 | 11:18 PM - Posted by Jerald Tapalla (not verified)

This is the first time I just sit and read a long article with my focus just on it. Very nice article, very informative especially for me who is new to this kind of stuff. Thanks for this.

October 22, 2013 | 11:38 PM - Posted by Josh Walrath

Thanks for reading the entire thing!  Ryan will thank you as well!

October 22, 2013 | 11:57 PM - Posted by Onehourleft

Great writing Josh. Also it was nice to visit your archives for the first time. I enjoyed both articles.

October 23, 2013 | 01:29 AM - Posted by MeezyATL (not verified)

Some great articles from the PC Per staff this week. Keep up the good work.

October 23, 2013 | 05:06 AM - Posted by thinkbiggar (not verified)

Can you run that thing in SLI? Also did it cause you to loose all your hair?
I bet the prices stayed the same but not with inflation. Don't tell marketing people about inflation. Once they learn about it we are all screwed.

October 23, 2013 | 01:11 PM - Posted by Josh Walrath

I lost my hair because I got married and had kids.

October 23, 2013 | 07:01 AM - Posted by WantT100 (not verified)

This is a stunning article, this is why I visit Pcper every day. Ryan give the man a bonus!

This article is up there with Scott's "The Windows You Love is Gone" stunner a year ago.
http://www.pcper.com/reviews/Editorial/Windows-You-Love-Gone

October 23, 2013 | 08:13 AM - Posted by Anonymous (not verified)

These kind of delays are to be expected. The smaller you go, the indiviual effects become that much ore pronounced. Instead of treating the design as a whole or in smaller but relatively large units, more research needs to be done in examining each and every change occuring within the system. Very time consuming and expensive. I will not be surprised if there are further delays. The break-neck speed of development had to come to an end some time.

Not disappointed about delays but very much expected. Can´t keep throwing money and expect it to pay dividends immediatly. My 2 cents.

October 23, 2013 | 12:46 PM - Posted by Josh Walrath

Yup, you are likely correct.  What we often don't hear about is how closely the fab engineers work with the designers.  The amount of back and forth work and information they do is pretty staggering, especially with these next generation nodes.  This simply isn't a "we are finished with the design, send it to the Fab guys and they can figure out the rest!" situation anymore.

We are also seeing the pure-play guys working to amortize their investments in current process nodes... because the next gen stuff is so expensive.  Gotta pay those bills.  They only hope that Intel will slow down, cause those guys don't clear $3 billion a quarter like Intel does.

October 23, 2013 | 10:25 AM - Posted by blitzio

Amazing article Josh, thank you for an informative read. I feel thoroughly educated.

October 23, 2013 | 10:29 AM - Posted by Max KreFey

Great article Josh! Thank you from cold mother Russia! :D

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