More on JMicron's new SSD controller
Subject: Storage | May 31, 2009 - 10:36 PM | Allyn Malventano
If you listen to our Wednesday fun on Leo Laporte's TWIT network or to our weekly podcast, you might have caught some initial tidbits about a new SSD controller in the works over at JMicron. I did a bit more digging to bring you a scoop worthy of sufficient detail.
The controller uses an ARM 9 based CPU and has 8 independent flash control channels, each performing hardware ECC capable of correcting 24 bits per kByte. This is the first JMicron SSD controller to implement hardware ECC. Also new are hardware-based 128 bit AES encryption and DRAM caching. Another bonus is the integrated USB 2.0 controller, which comes in very handy for imaging a current install over to the SSD prior to installation. The USB capability can alternatively be used to convert it into a jumbo-sized jump drive as long as you bring along a mini-USB cable.
JMicron will likely release a lower end JMF611 controller in tandem with the 612, which will share all of the above features but will be limited to 4 flash channels (and therefore half the throughput). JMicron's roadmap also includes SATA 3.0 and USB 3.0 support in products to be released in the first half of 2010. Given that Indilinx can nearly saturate SATA 2.0 with only 4 channels on their ARM controller, the JMF612 should be a vast improvement over the previous generation 601 and 602 / 602b controllers.
Lets hope the ARM controller and cache help JMicron overcome the shortcomings of their previous generation controllers. Their current 'press' numbers are 230 MB/sec reads and 150-200 MB/sec writes, with IOPS figures pushing 15k/sec. More to follow when we get our hands on one.
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