That RAM is stacked
Subject: General Tech | November 28, 2013 - 06:48 PM | Jeremy Hellstrom
Tagged: DRAM, HMC, hybrid memory cubes, micron, TSV
Hybrid Memory Cubes are DRAM stacked in layers with logic on the bottom layer to decide which memory layer to address commands to whic is being developed by a team that includes Altera, ARM, IBM, SK Hynix, Micron, Open-Silicon, Samsung and Xilinix. This is intended to give DRAM enhanced parallelization which will help it keep up with today's multi-cored processors. Micron's example which the Register takes a look at here claims up to 10 GB/sec (80 Gb/sec) of bandwidth from each of the 16 vaults present on the chip, a vault being an area of memory on a layer. That compares favourably to the maximum theoretical JEDEC speed of DDR3-1333 which is just a hair over 10GB/s. Read more here.
"Dratted multi-core CPUs. DRAM is running into a bandwidth problem. More powerful CPUs has meant that more cores are trying to access a server’s memory and the bandwidth is running out.
One solution is to stack DRAM in layers above a logic base layer and increase access speed to the resulting hybrid memory cubes (HMC), and Micron has done just that."
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