Intel Launches High-Performance 90-Nanometer Multi-Level-Cell Nor Flash Memory For Multimedia Handse
Subject: General Tech | November 17, 2005 - 01:10 PM | Jeremy Hellstrom
SANTA CLARA, Calif., Nov. 17, 2005 — Intel Corporation today announced it is shipping in volume the industry's first 90-nanometer (nm) multi-level cell (MLC) NOR flash memory device. The new Intel StrataFlashÂ® Cellular Memory (M18) delivers faster performance, higher density and lower power consumption than the previous 130nm version to meet the increasing demand for feature-rich cell phones equipped with cameras, color screens, Web browsing and video.
'Flash memory is one of the driving technologies in enabling the next generation of cell phone applications,' said Darin Billerbeck, vice president and general manager, Intel Flash Products Group. 'The M18 delivers to cellular designers the unique combination of performance, density and low power required for today's phones. Moreover, the M18 is built on Intel's reliable and cost-effective fifth generation MLC technology and 90nm process lithography.'
The M18 offers the fastest read speeds in the industry, enabling the new flash memory to operate at the same bus frequency as next-generation cellular chipsets — up to 133MHz. This speeds user application execution because the interaction between the chipset and memory operation is faster than in the 130nm version. With write speeds of up to 0.5MB/second, the M18 supports 3MP (mega pixel) cameras and MPEG4 video. OEMs benefit from lower production costs that result from factory programming speeds of up to three times faster than prior 130-nm versions. The M18 consumes one-third the energy to program and about half the energy to erase than prior generation products, and offers the new Deep Power Down operation mode, all for improved battery life. The M18 also increases the NOR flash density reach, with single chip solutions of 256 Mb and 512 Mb and standard stacked package solutions up to 1 Gb. Intel's industry-leading standard stacks combine NOR and RAM in mul! tiple bus archite= ures, and improve OEM time-to-market and supply-line flexibility.
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