Sorry this probably wont be a usual thing, but we'll see how often I can do it. I stayed at the office until 2am to get it up this quickly :)

suppose that would make sense

Full fat gaming APUs, with plenty of wide parallel traces from CPU to GPU, so imagine a 4096+ bit connection between CPU and GPU traced out on the interposer's silicon substrate. And that wide connection between CPU and GPU will be in addition to the memory controller's 4, 1024 bit wide channels to the HBM Memory stacks. So AMD could in essence wire up the CPU(separately fabricated) to a GPU(separately fabricated) directly with no need for any intermediary and latency inducing PCI/other outside protocols with the CPU able to communicate directly with the GPU.

Imagine being able to transfer 4096+ bit blocks of code/data directly from the CPU to GPU, and probably send that data directly to the GPUs cache for even faster than any memory transfer should that data/code be needed in a top priority manner. Those HPC/Supercomputer exascale grants that Uncle Sam has been spaffing across the computing industry to AMD and others will see this very interposer technology used for high powered gaming APUs.

AMD has an Exascale design with 32 Zen cores and FPGAs added to the HBM stacks between the HBM's memory controller die on the bottom of the stack, and the HBM memory dies above. So Maybe a high powered Gaming APU with a little reprogrammable FPGA processing help distributed on the HBM stacks. So on an interposer say for a consumer SKU with 12 Zen cores on its Die, wired up directly to a big fat Arctic Islands/Greenland GPU with plenty of ACE units, with the Zen CPU able to pass whole multi-thousands of byte blocks of code/data directly to the GPU.

With the interposer hosting tens of thousands of traces, I'd imagine that the CPU's and the GPU's processor Caches could be directly wired up so that a CPU would just have to write to its cache and have that cache write directly mirrored, or routed, to the GPU cache memory without the CPU having to stop what it's doing to initiate a data transfer, the whole transfer managed by the shared cache coherency circuity on the CPU and GPU, no extra latency inducing PCI, Main Memory, or other steps required.

That GDDR5, or GDDR6 memory is still going to have to be connected by much narrower memory channel's, and GDDR/whatever will still have to be clocked much higher to achieve HBM's effective bandwidth at HBM's much more power saving speed of 500Mhz for HBM1, and 1Ghz for HBM2, and HBM clocks memory transfers and double data clock rates, just like DDR memory, only HBM has a much wider 4, 1024 bit wide channels. So that GDDR5X/GDDR6 is still going to be a power hog, and a PCB space hog(for chips, and PCB traces)!

High powered gaming APU's will be made, derived from the HPC/Workstation and exascale computing APU technology that AMD is developing for those markets.

ditto that. See my comment above.