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Inspur Readies Tianhe-2 Supercomputer With 54 Petaflop Theoretical Peak Performance

Subject: Systems | June 3, 2013 - 09:27 PM |
Tagged: Xeon Phi, tianhe-2, supercomputer, Ivy Bridge, HPC, China

A powerful new supercomputer constructed by Chinese company Inspur is currently in testing at the National University of Defense Technology. Called the Tianhe-2, the new supercomputer has 16,000 compute nodes and approximately 54 Petaflops of peak theoretical compute performance.
Destined for the National Supercomputer Center in Guangzhou, China, the open HPC platform will be used for education and research projects. The Tianhe-2 is composed of 125 racks with 128 compute nodes in each rack.

The compute nodes are broken down into two types: CPM and APU modules. One of each node type makes up a single compute board. The CPM module hosts four Intel Ivy Bridge processors, 128GB system memory, and a single Intel Xeon Phi accelerator card with 8GB of its own memory. Each APU module adds five Xeon Phi cards to every compute board. The compute boards (a CPM module + a APU module) contain two NICs that connect the various compute boards with Inspur's custom THExpress2 high bandwidth interconnects. Finally, the Tianhe-2 supercomputer will have access to 12.4 Petabytes of storage that is shared across all of the compute boards.

In all, the Tianhe-2 is powered by 32,000 Intel Ivy Bridge processors, 1.024 Petabytes of system memory (not counting Phi dedicated memory--which would make the total 1.404 PB), and 48,000 Intel Xeon Phi MIC (Many Integrated Cores) cards. That is a total of 3,120,000 processor cores (though keep in mind that number is primarily made up of the relatively simple individual Phi cores as there are 57 cores to each Phi card).

Artist Rendition of Inspur-built Tianhe-2 Chinese Supercomputer.png

Inspur claims up to 3.432 TFlops of peak compute performance per compute node (which, for simplicity they break down as one node is 2 Ivy Bridge chips, 64GB memory, and 3 Xeon Phi cards although the two compute modules that make up a node are not physically laid out that way) for a total theoretical potential compute power of 54,912 TFlops (or 54.912 Petaflops) across the entire supercomputer. In the latest Linpack benchmark run, researchers saw up to 63% efficiency in attaining peak performance -- 30.65 PFlops out of 49.19 PFlops peak/theoretical performance -- when only using 14,336 nodes with 50GB RAM each. Further testing and optimization should improve that number, and when all nodes are brought online the real world performance will naturally be higher than the current benchmarks. With that said, the Tianhe-2 is already besting Cray's TITAN, which is promising (though I hope Cray comes back next year and takes the crown again, heh).

In order to keep all of this hardware cool, Inspur is planning a custom liquid cooling system using chilled water. The Tianhe-2 will draw up to 17.6 MW of power under load. Once the liquid cooling system is implemented the supercomputer will draw 24MW while under load.
This is an impressive system, and an interesting take on a supercomputer architecture considering the rise in popularity of heterogeneous architectures that pair massive numbers of CPUs with graphics processing units (GPUs).

The Tianhe-2 supercomputer will be reconstructed at its permanent home at the National Supercomputer Center in Guangzhou, China once the testing phase is finished. It will be one of the top supercomputers in the world once it is fully online! HPC Wire has a nice article with slides an further details on the upcoming processing powerhouse that is worth a read if you are into this sort of HPC stuff.

Also read: Cray unveils the TITAN supercomputer.

Source: HPC Wire

AMD's new FirePro S10000 sports two GPUs

Subject: General Tech, Graphics Cards | November 13, 2012 - 01:17 PM |
Tagged: amd, Intel, firepro, firepro s10000, HPC, Xeon Phi, 3120A, 5110P, Knight's Corner

AMD's new Tahiti based FirePro S10000 sports a little more than just a GPU upgrade it sports two GPU updates as this is a dual GPU card.  According to The Register it should run about $3,600 and need 375W to perform, numbers which make it a more efficient card than the S9000 even though it needs significantly more cash and power to run.  It is a 2 slot card, a necessity in the server and workstation world and while it does not support CrossFire it does support EyeFinity with its DVI port and four Mini DisplayPorts.

elreg_amd_firepro_s10000.jpg

The Register also got some news about Xeon Phi, Intel's answer to the HPC cards on offer from AMD and Intel.  Knights Corner is the evolution of Larrabee into an actual product, in this case two 62 core cards though not all of the cores are active. The passively cooled 5110P has 60 cores running at 1.053GHz, while the 3120A has 57 cores clocked slightly higher at 1.1GHz and sports a fan.  Both cards produce just over a teraflop of double precision floating point math, compared to the 1.48 teraflops offered by AMD's S10000 or the 1.3 offered by the Tesla K20x. Check out more on these coprocessors at The Register.

elreg_intel_xeon_phi_die_shot.jpg

"With the FirePro S10000, not only is the GPU geared down to 825MHz, but the memory is similarly downshifted to 5GHz. The memory interface is 384-bit wide on each GPU, with two blocks of GDDR5 memory yielding a total of 6GB. (This could be a little skinny on the memory for some HPC workloads, given that the S9000 card has 6GB of memory for one Tahiti GPU.) Each GPU can access 240GB/sec of memory bandwidth linking to each 3GB chunk of GDDR5 memory.

Because the card is double-stuffed, it can deliver a very impressive 5.91 teraflops SP and 1.48 teraflops DP in peak floating point oomph."

Here is some more Tech News from around the web:

Tech Talk

Source: The Register

Fee PHI fo fum; Intel changes the smell of a Pentium

Subject: General Tech | September 5, 2012 - 03:49 PM |
Tagged: Xeon Phi, xeon, larrabee, knights corner, Intel, hot chips

The Register is back with more information from Hot Chips about Intel's Xeon Phi coprocessor, which seems to be much more than just a GPU in drag.  Inside the shell you will find at least 50 cores and at least 8GB of GDDR5 graphics, wwith the cores being very heavily modified 22-nanometer Tri-Gate process Pentium P54C chips clocked somewhere between 1.2-1.6GHz.  There is a brand new Vector Processing Unit which processes 512-bit SIMD instructions and sports an Extended Math Unit to handle calculations with hardware not software.  Read on for more details about the high-speed ring interconnects that allow these chips to communicate among themselves and with the Xeon server it will be a part of.

ElReg_intel_xeon_phi_block_diagram.jpg

"Intel has been showing off the performance of the "Knights Corner" x86-based coprocessor for so long that it's easy to forget that it is not yet a product you can actually buy. Back in June, Knights Corner was branded as the "Xeon Phi", making it clear that Phi was a Xeon coprocessor even if it does not bear a lot of resemblance to the Xeon processors at the heart of the vast majority of the world's servers."

Here is some more Tech News from around the web:

Tech Talk

Source: The Register

A lot of little Phi coprocessors lightens the load

Subject: General Tech | August 31, 2012 - 02:43 PM |
Tagged: Intel, xeon, Xeon Phi, hot chips, larrabee

The Xeon Phi is not Larrabee but it does give a chance to remind people that Intel did at one time swear we would be seeing huge results from a lot of strung together Pentium chips.  Nor is Many Integrated Cores the same as AMD's Magny-cours, although you can be forgiven if that thought popped into your head.  Instead the Xeon Phi is a co-processor that will have 50 or more 512-bit SIMD architecture based processors, each with 512KB of Level 2 cache.  These cores are comparatively slow on their own but have been designed to spread tasks over dozens of cores for parallel processing to make up for the lack of individual power.  Intel sees Phi as a way to create HPC servers which will be physically smaller than one based solely on traditional Xeon based servers as well as being more efficient.  There is still a lot more we need to learn about these chips; until then you can check out The Inquirer's article on Intel's answer to NVIDIA and AMD's HPC cards.

Xeon_Phi_PCIe_Card.jpg

"CHIPMAKER Intel revealed some architectural details of its upcoming Xeon Phi accelerator at the Hotchips conference, saying that the chip will feature 512-bit SIMD units."

Here is some more Tech News from around the web:

Tech Talk

Source: The Inquirer

Intel Introduces Xeon Phi: Larrabee Unleashed

Subject: Processors | June 19, 2012 - 11:46 AM |
Tagged: Xeon Phi, xeon e5, nvidia, larrabee, knights corner, Intel, HPC, gpgpu, amd

Intel does not respond well when asked about Larabee.  Though Intel has received a lot of bad press from the gaming community about what they were trying to do, that does not necessarily mean that Intel was wrong about how they set up the architecture.  The problem with Larrabee was that it was being considered as a consumer level product with an eye for breaking into the HPC/GPGPU market.  For the consumer level, Larrabee would have been a disaster.  Intel simply would not have been able to compete with AMD and NVIDIA for gamers’ hearts.
 
The problem with Larrabee and the consumer space was a matter of focus, process decisions, and die size.  Larrabee is unique in that it is almost fully programmable and features really only one fixed function unit.  In this case, that fixed function unit was all about texturing.    Everything else relied upon the large array of x86 processors and their attached vector units.  This turns out to be very inefficient when it comes to rendering games, which is the majority of work for the consumer market in graphics cards.  While no outlet was able to get a hold of a Larrabee sample and run benchmarks on it, the general feeling was that Intel would easily be a generation behind in performance.  When considering how large the die size would have to be to even get to that point, it was simply not economical for Intel to produce these cards.
 
phi_01.jpg
 
Xeon Phi is essentially an advanced part based on the original Larrabee architecture.
 
This is not to say that Larrabee does not have a place in the industry.  The actual design lends itself very nicely towards HPC applications.  With each chip hosting many x86 processors with powerful vector units attached, these products can provide tremendous performance in HPC applications which can leverage these particular units.  Because Intel utilized x86 processors instead of the more homogenous designs that AMD and NVIDIA use (lots of stream units doing vector and scalar, but no x86 units or a more traditional networking fabric to connect them).  This does give Intel a leg up on the competition when it comes to programming.  While GPGPU applications are working with products like OpenCL, C++ AMP, and NVIDIA’s CUDA, Intel is able to rely on many current programming languages which can utilize x86.  With the addition of wide vector units on each x86 core, it is relatively simple to make adjustments to utilize these new features as compared to porting something over to OpenCL.
 
So this leads us to the Intel Xeon Phi.  This is the first commercially available product based on an updated version of the Larrabee technology.  The exact code name is Knights Corner.  This is a new MIC (many integrated cores) product based on Intel’s latest 22 nm Tri-Gate process technology.  The details are scarce on how many cores this product actually contains, but it looks to be more than 50 of a very basic “Pentium” style core;  essentially low die space, in-order, and all connected by a robust networking fabric that allows fast data transfer between the memory interface, PCI-E interface, and the cores.
 
intelphi.jpg
 
Each Xeon Phi promises more than 1 TFLOP of performance (as measured by Linpack).  When combined with the new Xeon E5 series of processors, these products can provide a huge amount of computing power.  Furthermore, with the addition of the Cray interconnect technology that Intel acquired this year, clusters of these systems could provide for some of the fastest supercomputers on the market.  While it will take until the end of this year at least to integrate these products into a massive cluster, it will happen and Intel expects these products to be at the forefront of driving performance from the Petascale to the Exascale.
 
phi_02.jpg
 
These are the building blocks that Intel hopes to utilize to corner the HPC market.  Providing powerful CPUs and dozens if not hundreds of MIC units per cluster, the potential computer power should bring us to the Exascale that much sooner.
 
Time will of course tell if Intel will be successful with Xeon Phi and Knights Corner.  The idea behind this product seems sound, and the addition of powerful vector units being attached to simple x86 cores should make the software migration to massively parallel computing just a wee bit easier than what we are seeing now with GPU based products from AMD and NVIDIA.  The areas that those other manufacturers have advantages over Intel are that of many years of work with educational institutions (research), software developers (gaming, GPGPU, and HPC), and industry standards groups (Khronos).  Xeon Phi has a ways to go before being fully embraced by these other organizations, and its future is certainly not set in stone.  We have yet to see 3rd party groups get a hold of these products and put them to the test.  While Intel CPUs are certainly class leading, we still do not know of the full potential of these MIC products as compared to what is currently available in the market.
 

The one positive thing for Intel’s competitors is that it seems their enthusiasm for massively parallel computing is justified.  Intel just entered that ring with a unique architecture that will certainly help push high performance computing more towards true heterogeneous computing. 

Source: Intel

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