Subject: General Tech | September 18, 2014 - 01:59 PM | Ken Addison
Tagged: windows 9, video, TSV, supernova, raptr, r9 390x, podcast, p3700, nvidia, Intel, idf, GTX 980, evga, ECS, ddr4, amd
PC Perspective Podcast #318 - 09/18/2014
Join us this week as we discuss GTX 980 and R9 390X Rumors, Storage News from IDF, ADATA SP610 SSDs and more!
The URL for the podcast is: http://pcper.com/podcast - Share with your friends!
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Hosts: Ryan Shrout, Jeremy Hellstrom, Josh Walrath, and Allyn Malventano
Program length: 1:33:48
Week in Review:
News items of interest:
Hardware/Software Picks of the Week:
Allyn: Windows Server 2012 R2 Storage Spaces goodness (updated features)
Subject: Storage, Shows and Expos | September 10, 2014 - 03:34 PM | Allyn Malventano
Tagged: TSV, Through Silicon Via, memory, idf 2014, idf
If you're a general computer user, you might have never heard the term "Through Silicon Via". If you geek out on photos of chip dies and wafers, and how chips are assembled and packaged, you might have heard about it. Regardless of your current knowledge of TSV, it's about to be a thing that impacts all of you in the near future.
Let's go into a bit of background first. We're going to talk about how chips are packaged. Micron has an excellent video on the process here:
The part we are going to focus on appears at 1:31 in the above video:
This is how chip dies are currently connected to the outside world. The dies are stacked (four high in the above pic) and a machine has to individually wire them to a substrate, which in turn communicates with the rest of the system. As you might imagine, things get more complex with this process as you stack more and more dies on top of each other:
16 layer die stack, pic courtesy NovaChips
...so we have these microchips with extremely small features, but to connect them we are limited to a relatively bulky process (called package-on-package). Stacking these flat planes of storage is a tricky thing to do, and one would naturally want to limit how many of those wires you need to connect. The catch is that those wires also equate to available throughput from the device (i.e. one wire per bit of a data bus). So, just how can we improve this method and increase data bus widths, throughput, etc?
Before I answer that, let me lead up to it by showing how flash memory has just taken a leap in performance. Samsung has recently made the jump to VNAND:
By stacking flash memory cells vertically within a die, Samsung was able to make many advances in flash memory, simply because they had more room within each die. Because of the complexity of the process, they also had to revert back to an older (larger) feature size. That compromise meant that the capacity of each die is similar to current 2D NAND tech, but the bonus is speed, longevity, and power reduction advantages by using this new process.
I showed you the VNAND example because it bears a striking resemblance to what is now happening in the area of die stacking and packaging. Imagine if you could stack dies by punching holes straight through them and making the connections directly through the bottom of each die. As it turns out, that's actually a thing:
Subject: General Tech | November 28, 2013 - 01:48 PM | Jeremy Hellstrom
Tagged: DRAM, HMC, hybrid memory cubes, micron, TSV
Hybrid Memory Cubes are DRAM stacked in layers with logic on the bottom layer to decide which memory layer to address commands to whic is being developed by a team that includes Altera, ARM, IBM, SK Hynix, Micron, Open-Silicon, Samsung and Xilinix. This is intended to give DRAM enhanced parallelization which will help it keep up with today's multi-cored processors. Micron's example which the Register takes a look at here claims up to 10 GB/sec (80 Gb/sec) of bandwidth from each of the 16 vaults present on the chip, a vault being an area of memory on a layer. That compares favourably to the maximum theoretical JEDEC speed of DDR3-1333 which is just a hair over 10GB/s. Read more here.
"Dratted multi-core CPUs. DRAM is running into a bandwidth problem. More powerful CPUs has meant that more cores are trying to access a server’s memory and the bandwidth is running out.
One solution is to stack DRAM in layers above a logic base layer and increase access speed to the resulting hybrid memory cubes (HMC), and Micron has done just that."
Here is some more Tech News from around the web:
- Prolonged Ivy Bridge life-cycle affects Intel 2014 CPU roadmap @ DigiTimes
- Repairing Dead USB Flash Drives @ Hack a Day
- Globalfoundries gearing up for high-volume MEMS manufacturing @ DigiTimes
- Gigabyte expected to post 28-year shipments high of 21 million motherboards in 2013 @ DigiTimes
- THOUSANDS of Ruby on Rails sites leave logins lying around @ The Register
- How to Remote Control Your Camera with Darktable on Linux @ Linux.com