Some dense reading for your morning about N3XT and nanotube based processors

Subject: General Tech | December 17, 2015 - 12:35 PM |
Tagged: N3XT, nanotubes, TSV

The achillies heel of processing density is heat and how to radiate it away from the parts doing the work, which is why processors and memory tend to be very flat.  This has change, we have begun to see 3D VNAND become common on the marketplace thanks to reduced heat generation and a variety of arcane tricks some of which Al explained last year.  Processors offer a more significant challenge, the TDP is much larger than that of flash and hotspots are more common and have a much more drastic effect on performance.  They can also be more difficult to fabricate; there is quite a trick to baking the interior of the chip without overcooking the external layers

Stanford University is working on what they call Nano-Engineered Computing Systems Technology, or N3XT which is working on Through Silicon Vias for processors. If successful this would allow a similar structure to current 3D VNAND on a processor which would vastly increase processing density.  The lower temperatures required to fab carbon nanotube transistors may just be what the industry has needed.  Make sure your brain is turned on and read on at The Inquirer.

carbon-nanotubes-n3xt-tech-540x334.jpeg

"One way in which Stanford University is exploring this is by using carbon nanotube technology in high-rise chip architecture processes. Working alongside other universities, Stanford engineers have created this new technology, which it calls Nano-Engineered Computing Systems Technology, or N3XT."

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Source: The Inquirer

Samsung Announces Mass Production of 128GB DDR4 Sticks

Subject: Memory | November 26, 2015 - 05:23 PM |
Tagged: TSV, Samsung, enterprise, ddr4

You may remember Allyn's article about TSV memory back from IDF 2014. Through this process, Samsung and others are able to stack dies of memory onto a single package, which can increase density and bandwidth. This is done by punching holes through the dies and connecting them down to the PCB. The first analogy that comes to mind is an elevator shaft, but I'm not sure how accurate that is.

tsv-side-on.JPG

Anyway, Samsung has been applying it to enterprise-class DDR4 memory, which leads to impressive capacities. 64GB sticks, individual sticks, were introduced in 2014. This year, that capacity doubles to 128GB. The chips are fabricated at 20nm and each contain 8Gb (1GB) per layer. Each stick contains 36 packages of four chips.

At the end of their press release, Samsung also mentioned that they intend to expand their TSV technology into “HBM and consumer products.”

Source: Samsung

Podcast #318 - GTX 980 and R9 390X Rumors, Storage News from IDF, ADATA SP610 SSDs and more!

Subject: General Tech | September 18, 2014 - 01:59 PM |
Tagged: windows 9, video, TSV, supernova, raptr, r9 390x, podcast, p3700, nvidia, Intel, idf, GTX 980, evga, ECS, ddr4, amd

PC Perspective Podcast #318 - 09/18/2014

Join us this week as we discuss GTX 980 and R9 390X Rumors, Storage News from IDF, ADATA SP610 SSDs and more!

You can subscribe to us through iTunes and you can still access it directly through the RSS page HERE.

The URL for the podcast is: http://pcper.com/podcast - Share with your friends!

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Hosts: Ryan Shrout, Jeremy Hellstrom, Josh Walrath, and Allyn Malventano

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IDF 2014: Through Silicon Via - Connecting memory dies without wires

Subject: Storage, Shows and Expos | September 10, 2014 - 03:34 PM |
Tagged: TSV, Through Silicon Via, memory, idf 2014, idf

If you're a general computer user, you might have never heard the term "Through Silicon Via". If you geek out on photos of chip dies and wafers, and how chips are assembled and packaged, you might have heard about it. Regardless of your current knowledge of TSV, it's about to be a thing that impacts all of you in the near future.

Let's go into a bit of background first. We're going to talk about how chips are packaged. Micron has an excellent video on the process here:

The part we are going to focus on appears at 1:31 in the above video:

die wiring.png

This is how chip dies are currently connected to the outside world. The dies are stacked (four high in the above pic) and a machine has to individually wire them to a substrate, which in turn communicates with the rest of the system. As you might imagine, things get more complex with this process as you stack more and more dies on top of each other:

chip stacking.png

16 layer die stack, pic courtesy NovaChips

...so we have these microchips with extremely small features, but to connect them we are limited to a relatively bulky process (called package-on-package). Stacking these flat planes of storage is a tricky thing to do, and one would naturally want to limit how many of those wires you need to connect. The catch is that those wires also equate to available throughput from the device (i.e. one wire per bit of a data bus). So, just how can we improve this method and increase data bus widths, throughput, etc?

Before I answer that, let me lead up to it by showing how flash memory has just taken a leap in performance. Samsung has recently made the jump to VNAND:

vnand crop--.png

By stacking flash memory cells vertically within a die, Samsung was able to make many advances in flash memory, simply because they had more room within each die. Because of the complexity of the process, they also had to revert back to an older (larger) feature size. That compromise meant that the capacity of each die is similar to current 2D NAND tech, but the bonus is speed, longevity, and power reduction advantages by using this new process.

I showed you the VNAND example because it bears a striking resemblance to what is now happening in the area of die stacking and packaging. Imagine if you could stack dies by punching holes straight through them and making the connections directly through the bottom of each die. As it turns out, that's actually a thing:

tsv cross section.png

Read on for more info about TSV!

That RAM is stacked

Subject: General Tech | November 28, 2013 - 01:48 PM |
Tagged: DRAM, HMC, hybrid memory cubes, micron, TSV

Hybrid Memory Cubes are DRAM stacked in layers with logic on the bottom layer to decide which memory layer to address commands to whic is being developed by a team that includes Altera, ARM, IBM, SK Hynix, Micron, Open-Silicon, Samsung and Xilinix.  This is intended to give DRAM enhanced parallelization which will help it keep up with today's multi-cored processors.  Micron's example which the Register takes a look at here claims up to 10 GB/sec (80 Gb/sec) of bandwidth from each of the 16 vaults present on the chip, a vault being an area of memory on a layer.  That compares favourably to the maximum theoretical JEDEC speed of DDR3-1333 which is just a hair over 10GB/s.  Read more here.

hmc_1.jpg

"Dratted multi-core CPUs. DRAM is running into a bandwidth problem. More powerful CPUs has meant that more cores are trying to access a server’s memory and the bandwidth is running out.

One solution is to stack DRAM in layers above a logic base layer and increase access speed to the resulting hybrid memory cubes (HMC), and Micron has done just that."

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Source: The Register