Subject: General Tech | September 27, 2012 - 01:46 PM | Ken Addison
Tagged: tlc, ssd, Sea Islands, Samsung, PSU, podcast, nvidia, IOPS, Intel, evga, amd, 840 pro, 840, 1500W
PC Perspective Podcast #220 - 09/27/2012
Join us this week as we talk about the Samsung 840 Pro SSD, a 1500W PSU from EVGA, AMD GPU leaks, and more!
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Hosts: Ryan Shrout, Josh Walrath, Jeremy Hellstrom, and Allyn Malvantano
Program length: 1:07:28
Podcast topics of discussion:
- Week in Reviews:
- 0:23:20 This Podcast is brought to you by MSI!
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Subject: General Tech | July 26, 2011 - 12:03 PM | Jeremy Hellstrom
Tagged: ssd, ocz, arm, tlc, sata 6Gps, Indilinx Everest
OCZ is never satisfied with the performance of their SSDs in general and their controllers specifically. After purchasing Indilinx to ensure that their controllers would be of high quality and designed to OCZ's specific needs, they've now been pushing Indilinx to improve on their controllers. That has lead to Everest, which has a dual core ARM processor and 400MHz DDR3 cache that can support up to 512MB. The controller is optimized for 8K writes which is perfect for the current flash utilized in SSDs. OCZ has also optimized the flash memory, developing Triple Level Cell (TLC) which has three layers as opposed to MLC which sports two. The controller will be backwards compatible, which is a good idea if OCZ wants to license the controller to other manufacturers, which makes sense as Everest should hit 200MT/s as compared to SandForce's current 166MT/s. There is more that this controller can do, click on over to The Register to read about it.
"OCZ is sampling a new flash controller that gives a picture of future solid state drives.
The company bought Indilinx for its solid state drive (SSD) controller technology in March this year and has now unveiled the Indilinx Everest controller platform.
It has a 6Gbit/s SATA III interface, a dual-core ARM processor and a number of enticing features, such as 3-bit multi-level cell (MLC) support. This is going to be called TLC, for triple-level cell, to distinguish it from today's MLC, which is 2-bit MLC."
Here is some more Tech News from around the web:
- Intel says it competes with Qualcomm not ARM @ The Inquirer
- Mozilla is developing a mobile operating system @ The Inquirer
- Running high-performance neural networks on a "gamer" GPU @ Ars Technica
- The Isostick @ Hack a Day
- Lawn warfare: Light Strike brings laser tag back home @ Ars Technica
- JMicron develops SATA 6Gbps controller IC for SSDs @ DigiTimes
- The TR Podcast 92: Fusion, the cloud, and dongles galore
- Sony Alpha NEX-C3 Review @ TechReviewSource
- Real World Labs And A.C.Ryan Joint Contest
Subject: Storage | April 27, 2011 - 10:06 PM | Allyn Malventano
Tagged: tlc, ssd, slc, ocz, mlc, flash
A while back, Intel and Micron jointly announced the beginnings of 20nm flash memory production, promising a 50% increase in die count per wafer (or a 50% reduction in per die production cost, depending on how you slice it). This shrink only did just that - shrink the die. Capacity remained at 64Gbit (8GB).
A few days ago IMFT also announced another way to shrink that die, but this time keeping with the now 'old' 25nm process. It turns out they have refined 25nm to the point where consumer-grade TLC flash can be produced. TLC is Triple-Level-Cell. While SLC (Single) holds 1 bit per cell, and MLC (Multi) holds two, TLC holds 3 bits per cell. Compared to the MLC 25nm dies, this gives a capacity increase without changing much else. IMFT, however, is happy with the 8GB 'sweet spot', so instead of jumping to a 12GB die of the same physical size, they are opting to instead shrink the current 25nm die to 131mm^2.
25nm TLC die, same 8GB capacity, but less area than the 25nm MLC die.
This gives Intel and Micron two options for ultimately reducing the price of flash - either by shrinking the process and getting more 8GB MLC dies out of a 20nm wafer, or by squeezing more bits into each cell of existing 25nm flash.
This is good stuff. Let's hope it gets even more SSD's into even more machines this holiday season.
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