AMD Zen Diagram Leaked and Analysis

Subject: Processors | April 27, 2015 - 06:06 PM |
Tagged: Zen, Steamroller, Kaveria, k12, Excavator, carrizo, bulldozer, amd

There are some pretty breathless analysis of a single leaked block diagram that is supposedly from AMD.  This is one of the first indications of what the Zen architecture looks like from a CPU core standpoint.  The block diagram is very simple, but looks in the same style as what we have seen from AMD.  There are some labels, but this is almost a 50,000 foot view of the architecture rather than a slightly clearer 10,000 foot view.

There are a few things we know for sure about Zen.  It is a clean sheet design that moves away from what AMD was pursuing with their Bulldozer family of cores.  Zen gives up CMT for SMT support for handling more threads.  The design has a cluster of four cores sharing 8 MB of L3 cache, with each core having access to 512 KB of L2 cache.  There is a lot of optimism that AMD can kick the trend of falling more and more behind Intel every year with this particular design.  Jim Keller is viewed very positively due to his work at AMD in the K7 through K8 days, as well as what he accomplished at Apple with their ARM based offerings.


One of the first sites to pick up this diagram wrote quite a bit about what they saw.  There was a lot of talk about, “right off the bat just by looking at the block diagram we can tell that Zen will have substantially higher single threaded performance compared to Excavator and the Bulldozer family.”  There was the assumption that because it had two 256-bit FMACs that it could fuse them to create a single 512 bit AVX product.

These assumptions are pretty silly.  This is a very simple block diagram that answers few very important questions about the architecture.  Yes, it shows 6 int pipelines, but we don’t know how many are address generation vs. execution units.  We don’t know how wide decode is.  We don’t know latency to L2 cache, much less how L3 is connected and shared out.  So just because we see more integer pipelines per core does not automatically mean, “Da, more is better, strong like tractor!”  We don’t know what improvements or simplifications we will see in the schedulers.  There is no mention of the front-end other than Fetch and Decode.  How about Branch Prediction?  What is the latency for the memory controller when addressing external memory?

Essentially, this looks like a simplified way of expressing to analysts that AMD is attempting to retain their per core integer performance while boosting floating point/AVX at a similar level.  Other than that, there is very little that can be gleaned from this simple block diagram.

Other leaks that are interesting concerning Zen are the formats that we will see these products integrated into.  One leak detailed a HPC aimed APU that features 16 Zen cores with 32 MB of L3 cache attached to a very large GPU.  Another leak detailed a server level chip that will support 32 cores and will be seen in 2P systems.  Zen certainly appears to be very flexible, and in ways it reminds me of a much beefier Jaguar type CPU.  My gut feeling is that AMD will get closer to Intel than it has been in years, and perhaps they can catch Intel by surprise with a few extra features.  The reality of the situation is that AMD is far behind and only now are we seeing pure-play foundries start to get even close to Intel in terms of process technology.  AMD is very much at a disadvantage here.

Still, the company needs to release new, competitive products that will refill the company coffers.  The previous quarter’s loss has dug into cash reserves, but AMD is still stable in terms of cash on hand and long term debt.  2015 will see new GPUs, an APU refresh, and the release of the new Carrizo parts.  2016 looks to be the make or break year with Zen and K12.

Edit 2015-04-28:  Thanks to SH STON we have a new slide that has been leaked from the same deck as this one.  This has some interesting info in that AMD may be going away from exclusive cache designs.  Exclusive was a good idea when cache was small and expensive, as data was not replicated through each level of cache (L1 was not replicated in L2 and L2 was not replicated in L3).  Intel has been using inclusive cache since forever, where data is replicated and simpler to handle.  Now it looks like AMD is moving towards inclusive.  This is not necessarily a bad thing as the 512 KB of L2 can easily handle what looks to be 128 KB of L1 and the shared 8 MB of L3 cache can easily handle the 2 MB of L2 data.  Here is the link to that slide.


The new slide in question.

Source: AMD

AMD Announces Carrizo and Carrizo-L SOCs

Subject: Processors | November 20, 2014 - 01:31 PM |
Tagged: amd, APU, carrizo, Carrizo-L, Kaveri, Excavator, Steamroller, SoC, Intel, mobile

AMD has certainly gone about doing things in a slightly different manner than we are used to.  Today they announced their two latest APUs which will begin shipping in the first half of 2015.  These APUs are running at AMD and are being validated as we speak.  AMD did not release many details on these products, but what we do know is pretty interesting.

Carrizo is based on the latest iteration of AMD’s CPU technology.  Excavator is the codename for these latest CPU cores, and they promise to be smaller and more efficient than the previous Steamroller core which powers the latest Kaveri based APUs.  Carrizo-L is the lower power variant which will be based on the Puma+ core.  The current Beema APU is based on the Puma architecture.


Roadmaps show that the Carrizo APUs will be 28 nm products, presumably fabricated by GLOBALFOUNDRIES.  Many were hoping that AMD would make the jump to 20 nm with this generation of products, but that does not seem to be the case.  This is not surprising due to the limitations of that particular process when dealing with large designs that require a lot of current.  AMD will likely be pushing for 16 nm FinFET for the generation of products after Carrizo.

The big Carrizo supposedly has a next generation GCN unit.  My guess here is that it will use the same design as we saw with the R9 285.  That particular product is a next generation unit that has improved efficiency.  AMD did not release how many GCN cores will be present in Carizzo, but it will be very similar to what we see now with Kaveri.  Carrizo-L will use the same GCN units as the previous generation Beema based products.


I believe AMD has spent a lot more time hand tuning Excavator instead of relying on a lot of automated place and route.  This should allow them to retain much of the performance of the part, all the while cutting down on transistor count dramatically.  Some rumors that I have seen point to each Excavator module being 40% smaller than Steamroller.  I am not entirely sure they have achieved that type of improvement, but more hand layout does typically mean greater efficiency and less waste.  The downside to hand layout is that it is extremely time and manpower intensive.  Intel can afford this type of design while AMD has to rely more on automated place and route.

Carrizo will be the first HSA 1.0 compliant SOC.  It is in fact an SOC as it integrates the southbridge functions that previously had been handled by external chips like the A88X that supports the current Kaveri desktop APUs.  Carrizo and Carrizo-L will also share the same infrastructure.  This means that motherboards that these APUs will be soldered onto are interchangeable.  One motherboard from the partner OEMs will be able to address multiple markets that will see products range from 4 watts TDP up to 35 watts.

Finally, both APUs feature the security processor that allows them access to the ARM TrustZone technology.  This is a very small ARM processor that handles the secure boot partition and handles the security requests.  This puts AMD on par with Intel and their secure computing solution (vPro).


These products will be aimed only at the mobile market.  So far AMD has not announced Carrizo for the desktop market, but when they do I would imagine that they will hit a max TDP of around 65 watts.  AMD claims that Carrizo is one of the biggest jumps for them in terms of power efficiency.  A lot of different pieces of technology have all come together with this product to make them more competitive with Intel and their process advantage.  Time will tell if this is the case, but for now AMD is staying relevant and pushing their product releases so that they are more consistently ontime.

Source: AMD
Subject: Processors
Manufacturer: AMD

Another Boring Presentation...?

In my old age I am turning into a bit of a skeptic.  It is hard to really blame a guy; we are surrounded by marketing and hype, both from inside companies and from their fans.  When I first started to listen in on AMD’s Core Innovation Update presentation, I was not expecting much.  I figured it would be a rehash of the past year, more talk about Mullins/Beema, and some nice words about some of the upcoming Kaveri mobile products.

I was wrong.

AMD decided to give us a pretty interesting look at what they are hoping to accomplish in the next three years.  It was not all that long ago that AMD was essentially considered road kill, and there was a lot of pessimism that Rory Read and Co. could turn AMD around.  Now after a couple solid years of growth, a laser-like focus on product development based on the IP strengths of the company, and a pretty significant cut of the workforce, we are seeing an AMD that is vastly different from the one that Dirk Meyers was in charge of (or Hector Ruiz for that matter).  Their view for the future takes a pretty significant turn from where AMD was even 8 years ago.  x86 certainly has a future for AMD, but the full-scale adoption of the ARM architecture looks to be what finally differentiates this company from Intel.

Look, I’m Amphibious!

AMD is not amphibious.  They are working on being ambidextrous.  Their goal is not only to develop and sell x86 based processors, but also be a prime moving force in the ARM market.  AMD has survived against a very large, well funded, and aggressive organization for the past 35 years.  They believe their experience here can help them break into, and thrive within, the ARM marketplace.  Their goals are not necessarily to be in every smartphone out there, but they are leveraging the ARM architecture to address high growth markets that have a lot of potential.


There are really two dominant architectures in the world with ARM and x86.  They power the vast majority of computing devices around the world.  Sure, we still have some Power and MIPS implementations, but they are dwarfed by the combined presence of x86 and ARM in modern devices.  The flexibility of x86 allows it to scale from the extreme mobile up to the highest performing clusters.  ARM also has the ability to scale in performance from handhelds up to the server world, but so far their introduction into servers and HPC solutions has been minimal to non-existent.  This is an area that AMD hopes to change, but it will not happen overnight.  A lot of infrastructure is needed to get ARM into that particular area.  Ask Intel how long it took for x86 to gain a handhold in the lucrative server and workstation markets.

Click here to read the entire article on AMD's Core Technology Update!

Subject: Processors
Manufacturer: AMD

More Details from Lisa Su

The executives at AMD like to break their own NDAs.  Then again, they are the ones typically setting these NDA dates, so it isn’t a big deal.  It is no secret that Kaveri has been in the pipeline for some time.  We knew a lot of the basic details of the product, but there were certainly things that were missing.  Lisu Su went up onstage and shared a few new details with us.


Kaveri will be made up of 4 “Steamroller” cores, which are enhanced versions of the previous Bulldozer/Trinity/Vishera families of products.  Nearly everything in the processor is doubled.  It now has dual decode, more cache, larger TLBs, and a host of other smaller features that all add up to greater single thread performance and better multi-threaded handling and performance.   Integer performance will be improved, and the FPU/MMX/SSE unit now features 2 x 128 bit FMAC units which can “fuse” and support AVX 256.

However, there was no mention of the fabled 6 core Kaveri.  At this time, it is unlikely that particular product will be launched anytime soon. 

Click to read the entire article here!

Subject: Editorial
Manufacturer: AMD

Retiring the Workhorses

There is an inevitable shift coming.  Honestly, this has been quite obvious for some time, but it has just taken AMD a bit longer to get here than many have expected.  Some years back we saw AMD release their new motto, “The Future is Fusion”.  While many thought it somewhat interesting and trite, it actually foreshadowed the massive shift from monolithic CPU cores to their APUs.  Right now AMD’s APUs are doing “ok” in desktops and are gaining traction in mobile applications.  What most people do not realize is that AMD will be going all APU all the time in the very near future.


We can look over the past few years and see that AMD has been headed in this direction for some time, but they simply have not had all the materials in place to make this dramatic shift.  To get a better understanding of where AMD is heading, how they plan to address multiple markets, and what kind of pressures they are under, we have to look at the two major non-APU markets that AMD is currently hanging onto by a thread.  In some ways, timing has been against AMD, not to mention available process technologies.

Click here to read the entire editorial!


hUMA has come with a weapon to slay the memory latency dragon

Subject: General Tech | April 30, 2013 - 01:23 PM |
Tagged: Steamroller, piledriver, Kaveri, Kabini, hUMA, hsa, GCN, bulldozer, APU, amd

AMD may have united GPU and CPU into the APU but one hurdle had remained until now, the the non-uniformity of memory access between the two processors.  Today we learned about one of the first successful HAS projects called Heterogeneous Uniform Memory Access, aka hUMA, which will appear in the upcoming Kaveri chip family.   The use of this new technology will allow the on-die CPU and GPU to access the same memory pool, both physical and virtual and any data passed between the two processors will remain coherent.  As The Tech Report mentions in their overview hUMA will not provide as much of a benefit to discrete GPUs, while they will be able to share address space the widely differing clock speeds between GDDR5 and DDR3 prevent unification to the level of an APU.

Make sure to read Josh's take as well so you can keep up with him on the Podcast.


"At the Fusion Developer Summit last June, AMD CTO Mark Papermaster teased Kaveri, AMD's next-generation APU due later this year. Among other things, Papermaster revealed that Kaveri will be based on the Steamroller architecture and that it will be the first AMD APU with fully shared memory.

Last week, AMD shed some more light on Kaveri's uniform memory architecture, which now has a snazzy marketing name: heterogeneous uniform memory access, or hUMA for short."

Here is some more Tech News from around the web:

Tech Talk

Subject: Processors
Manufacturer: AMD

heterogeneous Uniform Memory Access


Several years back we first heard AMD’s plans on creating a uniform memory architecture which will allow the CPU to share address spaces with the GPU.  The promise here is to create a very efficient architecture that will provide excellent performance in a mixed environment of serial and parallel programming loads.  When GPU computing came on the scene it was full of great promise.  The idea of a heavily parallel processing unit that will accelerate both integer and floating point workloads could be a potential gold mine in wide variety of applications.  Alas, the promise of the technology did not meet expectations when we have viewed the results so far.  There are many problems with combining serial and parallel workloads between CPUs and GPUs, and a lot of this has to do with very basic programming and the communication of data between two separate memory pools.


CPUs and GPUs do not share common memory pools.  Instead of using pointers in programming to tell each individual unit where data is stored in memory, the current implementation of GPU computing requires the CPU to write the contents of that address to the standalone memory pool of the GPU.  This is time consuming and wastes cycles.  It also increases programming complexity to be able to adjust to such situations.  Typically only very advanced programmers with a lot of expertise in this subject could program effective operations to take these limitations into consideration.  The lack of unified memory between CPU and GPU has hindered the adoption of the technology for a lot of applications which could potentially use the massively parallel processing capabilities of a GPU.

The idea for GPU compute has been around for a long time (comparatively).  I still remember getting very excited about the idea of using a high end video card along with a card like the old GeForce 6600 GT to be a coprocessor which would handle heavy math operations and PhysX.  That particular plan never quite came to fruition, but the idea was planted years before the actual introduction of modern DX9/10/11 hardware.  It seems as if this step with hUMA could actually provide a great amount of impetus to implement a wide range of applications which can actively utilize the GPU portion of an APU.

Click here to continue reading about AMD's hUMA architecture.

Subject: Processors
Manufacturer: Intel

Moving Towards BGA Only?

The sky is falling.  Does this mean that Chicken Little is panicking for no reason or is Chicken Little the Cassandra of our time?  It has been widely reported that Intel will not be offering the next generation Broadwell architecture as a LGA based product.  Broadwell is a 14 nm product that will integrate southbridge functions into the chip, making it essentially a SOC.  It will be offered only as a BGA only product, which means that it will be soldered onto a motherboard with no chance of being able to be swapped out.  Broadwell is the successor to the upcoming Haswell, itself a 22 nm product that features many architectural changes to both the CPU and graphics portion as compared to the current 22 nm Ivy Bridge.


Will Broadwell be the death of the desktop industry and enthusiasts?  Will LGA become as scarce as chicken teeth?  Will we ever see a product with a swappable CPU after 2014?

Broadwell is aimed at TDPs ranging from 10 watts to 57 watts.  Current high end Ivy Bridge parts max out at 77 watts and do not feature any southbridge type functionality.  So that means that another 5 to 7 watts are added in for the chipset when discussing basic system TDPs.  So we are looking at around 87 watts for a top end product when including SATA and USB functionality.  30 watts is a pretty big deal in OEM circles.  We see right off the bat that Intel is aiming this architecture at a slightly different market, or at least a changing marketplace.

The unease that we are seeing is essentially this; Intel appears to be trying to take more profits from this setup and pass more costs onto the motherboard industry.  This is not necessarily new for Intel, as they did this when transitioning to the LGA socket.  LGA sockets are more expensive and more troublesome for the motherboard manufacturers as compared to a more traditional pin based interface.  AMD continues to use pin based chips as this lowers the cost that is incurred by the motherboard manufacturers, and it also lowers overall support issues.  LGAs are pretty solid, but it is very easy to bend one or more of those contacts so that they in fact do not create a solid connection with the CPU.  This is something that is uncommon with pin based CPUS, but the downside of pin based is that it is more expensive to produce the CPU in the first place as compared to a LGA chip which only features the pads on the substrate of the CPU.

Continue reading our thoughts on Intel's move to BGA processors...

Piledrivers are elegant in comparison to Bulldozers

Subject: Processors | October 23, 2012 - 02:44 PM |
Tagged: vishera, Steamroller, piledriver, FX-8350, fx-8150, FX-6300, FX-6200, bulldozer, amd

The FX-8350 Vishera processor from AMD has finally arrived with 8 fully unlocked cores of polished Piledriver processing power.  With Piledriver there are no huge changes to the existing Bulldozer architecture, this is more of a polishing and optimizing the existing architecture and [H]ard|OCP's testing bears that out.  While faster than the previous generation FX-8150 it still lags behind Intel's Ivy Bridge processors, disappointing but certainly expected.  The unlocked cores do lend themselves somewhat to overclocking, with [H] hitting a stable 4.6GHz with all cores enabled, a 10% jump in frequency.  At that speed it does better when competing with Intel's offerings, until you overclock them as well at which point the comparative performance suffers somewhat.

Make sure to catch Josh's review, covering both the 8 core FX-8350 and the $132 FX-6300 which has a disabled module; bringing back memories of older AMD chips whose modules could be brought back to life.


"AMD's new Piledriver core technology should not be a surprise to any enthusiast as much of its "embargoed" information has already been exposed on the Net. Today we take the AMD FX series model 8350 desktop variant, code named Vishera, and look at it in an enthusiast way as we expose its IPC at 4GHz, and a bit of overclocking."

Here are some more Processor articles from around the web:


Source: [H]ard|OCP
Subject: Processors
Manufacturer: AMD

Bulldozer to Vishera


Bulldozer is the word.  Ok, perhaps it is not “the” word, but it is “a” word.  When AMD let that little codename slip some years back, AMD enthusiasts and tech journalists started to salivate about the possibilities.  Here was a unique and very new architecture that promised excellent single thread performance and outstanding multi-threaded performance all in a package that was easy to swallow and digest.  Probiotics for the PC.  Some could argue that the end product for Bulldozer and probiotics are the same, but I am not overly fond of writing articles containing four letter colorful metaphors.


The long and short of Bulldozer is that it was a product that was pushed out too fast, it had specifications that were too aggressive for the time, and it never delivered on the promise of the architecture.  Logically there are some very good reasons behind the architecture, but implementing these ideas into a successful product is another story altogether.  The chip was never able to reach the GHz range it was supposed to and stay within reasonable TDP limits.  To get the chip out in a timely manner, timings had to be loosened internally so the chip could even run.  Performance per clock was pretty dismal, and the top end FX-8150 was only marginally faster than the previous top end Phenom II X6 1100T.  In some cases, the X6 was still faster and a more competent “all around” processor.

There really was not a whole lot for AMD to do about the situation.  It had to have a new product, and it just did not turn out as nicely as they had hoped.  The reasons for this are legion, but simply put AMD is competing with a company that is over ten times the size, with the resulting R&D budgets that such a size (and margins) can afford.  Engineers looking for work are a dime a dozen, and Intel can hire as many as they need.  So, instead of respinning Bulldozer ad nauseum and releasing new speed grades throughout the year by tweaking the process and metal layer design, AMD let the product line sit and stagnate at the top end for a year (though they did release higher TDP models based on the dual module FX-4000 and triple module FX-6000 series).  Engineers were pushed into more forward looking projects.  One of these is Vishera.

Click here to read the rest of the Vishera Review!