Intel Roadmap Including Xeon E7 v2 Lineup

Subject: General Tech, Processors, Mobile | February 19, 2014 - 12:28 AM |
Tagged: Intel, SoC, atom, haswell, Haswell-E, Airmont, Ivy Bridge-EX

Every few months, we get another snapshot at some of Intel's products. This timeline has a rough placement for every segment, from their Internet of Things (IoT) product, the Quark, up to the Xeon E7 v2. While it covers from now through December, it is not designed to be a strict schedule and might contain an error or two.

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Image Credit: VR-Zone

First up is Ivy Bridge-EX (Xeon E7 v2). PCMag has an interesting rundown on these parts in depth, although some aspects are a little fuzzy. These 22nm-based chips range from 6 to 15 cores and can access up to 1.5TB of memory, per socket. Intel also claims they will support up to four times the I/O bandwidth for disk and network transactions. Naturally, they have all the usual virtualization and other features that are useful for servers. Most support Turbo Boost and all but one have Hyper-Threading Technology.

Jumping back to the VR-Zone editorial, the timeline suggests that the Quark X1000 will launch in April. As far as I can tell, this is new information. Quark is Intel's ultra low-end SoC that is designed for adding intelligence to non-computing devices. One example given by Intel at CES was a smart baby bottle warmer.

The refresh of Haswell is also expected to happen in April.

Heading into the third quarter, we should see Haswell-E make an appearance for the enthusiast desktop and moderately high-end server. This should be the first time since Sandy Bridge-E (2011) that expensive PCs get a healthy boost to single-threaded performance, clock for clock. Ivy Bridge-E, while a welcome addition, was definitely aimed at reducing power consumption.

Ending the year should be the launch of Airmont at 14nm. The successor to Silvermont, Airmont will be the basis of Cherry Trail tablets and lower end PCs at the very end of the year. Moorefield, which is Airmont for smartphones, is not listed on this roadmap and should not surface until 2015.

Source: VR-Zone
Author:
Subject: Editorial
Manufacturer: NVIDIA

It wouldn’t be February if we didn’t hear the Q4 FY14 earnings from NVIDIA!  NVIDIA does have a slightly odd way of expressing their quarters, but in the end it is all semantics.  They are not in fact living in the future, but I bet their product managers wish they could peer into the actual Q4 2014.  No, the whole FY14 thing relates back to when they made their IPO and how they started reporting.  To us mere mortals, Q4 FY14 actually represents Q4 2013.  Clear as mud?  Lord love the Securities and Exchange Commission and their rules.

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The past quarter was a pretty good one for NVIDIA.  They came away with $1.144 billion in gross revenue and had a GAAP net income of $147 million.  This beat the Street’s estimate by a pretty large margin.  As a response, trading of NVIDIA’s stock has gone up in after hours.  This has certainly been a trying year for NVIDIA and the PC market in general, but they seem to have come out on top.

NVIDIA beat estimates primarily on the strength of the PC graphics division.  Many were focusing on the apparent decline of the PC market and assumed that NVIDIA would be dragged down by lower shipments.  On the contrary, it seems as though the gaming market and add-in sales on the PC helped to solidify NVIDIA’s quarter.  We can look at a number of factors that likely contributed to this uptick for NVIDIA.

Click here to read the rest of NVIDIA's Q4 FY2014 results!

AMD's first Syst-ARM on a Chip Opteron will be here soon

Subject: General Tech | January 29, 2014 - 10:16 AM |
Tagged: SoC, seattle, opteron, arm, amd, A1100

The Opteron A1100 will be the name born by AMD's first SoC, which we knew previously as Seattle and is the first chip which will contain ARM Cortex A57 architecture working in tandem with AMDs.  It will be a full 64bit chip and will sport up to 4MB of shared L2 cache and 8MB of shared L3 cache and it will support of to four DIMMs of either DDR3 or DDR4 in dual channel with ECC.  It will boot using UEFI into a Linux environment based on Fedora and will be optimized to handle web front ends and data centre tasks.  As far as connectivity it will have 8 lanes of PCIe 3.0 and 8 SATA 3 ports. You can follow links from The Register to see the AMD Press Release.

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"CHIP DESIGNER AMD is preparing to sample its 64-bit ARM based server processors codenamed Seattle, which will be the company's first stab at a system on chip (SoC) design for data centre products."

Here is some more Tech News from around the web:

Tech Talk

Source: The Register

Nvidia's renamed Tegra K1 SoC uses Denver and Kepler

Subject: General Tech | January 6, 2014 - 11:08 AM |
Tagged: tegra k1, tegra, SoC, nvidia, kepler, k1, cortex a15, CES, arm, A15

Project X Logan K1 is the first big news out of CES from NVIDIA and represents a bit of a change from what we were expecting.  The current belief was that the SoC would have four 28nm Cortex A15 processors but that will only be one flavour of K1, a Denver based dual core version will also be released.  Those ARMv8 64-bit processors will natively handle 64 bit applications while the A15 version that The Tech Report had taken pictures of will be limited to 32 bit applications, though that will not matter in many mobile applications.   You should also check out Ryan's deep dive into the new Denver and Kepler version here.

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"In early 2011, during a CES press event, Nvidia revealed its Project Denver CPU initiative. On Sunday evening, at another CES press conference, the company provided a glimpse of the first Denver-based processor: the Tegra K1. This next-generation SoC features dual Denver CPU cores clocked at up to 2.5GHz. The cores were designed by Nvidia, and they're compatible with the 64-bit ARMv8 instruction set. They have a seven-way superscalar pipeline and a hefty 192KB of L1 cache."

Here is some more Tech News from around the web:

Tech Talk

 

Coverage of CES 2014 is brought to you by AMD!

PC Perspective's CES 2014 coverage is sponsored by AMD.

Follow all of our coverage of the show at http://pcper.com/ces!

Author:
Subject: Mobile
Manufacturer: NVIDIA

Once known as Logan, now known as K1

NVIDIA has bet big on Tegra.  Since the introduction of the SoC's first iteration, that much was clear.  With the industry push to mobile computing and the decreased importance of the classic PC design, developing and gaining traction with a mobile processor was not only an expansion of the company’s portfolio but a critical shift in the mindset of a graphics giant. 

The problem thus far is that while NVIDIA continues to enjoy success in the markets of workstation and consumer discrete graphics, the Tegra line of silicon-on-chip processors has faltered.  Design wins have been tough to come by. Other companies with feet already firmly planted on this side of the hardware fence continue to innovate and seal deals with customers.  Qualcomm is the dominant player for mobile processors with Samsung, MediaTek, and others all fighting for the same customers NVIDIA needs.  While press conferences and releases have been all smiles and sunshine since day one, the truth is that Tegra hasn’t grown at the rate NVIDIA had hoped.

Solid products based on NVIDIA Tegra processors have been released.  The first Google Nexus 7 used the Tegra 3 processor, and was considered the best Android tablet on the market by most, until it was succeeded by the 2013 iteration of the Nexus 7 this year.  Tegra 4 slipped backwards, though – the NVIDIA SHIELD mobile gaming device was the answer for a company eager to show the market they built compelling and relevant hardware.  It has only partially succeeded in that task.

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With today’s announcement of the Tegra K1, previously known as Logan or Tegra 5, NVIDIA hopes to once again spark a fire under partners and developers, showing them that NVIDIA’s dominance in the graphics fields of the PC has clear benefits to the mobile segment as well.  During a meeting with NVIDIA about Tegra K1, Dan Vivoli, Senior VP of marketing and a 16 year employee, equated the release of the K1 to the original GeForce GPU.  That is a lofty ambition and puts of a lot pressure on the entire Tegra team, not to mention the K1 product itself, to live up to.

Tegra K1 Overview

What we previously knew as Logan or Tegra 5 (and actually it was called Tegra 5 until just a couple of days ago), is now being released as the Tegra K1.  The ‘K’ designation indicated the graphics architecture that powers the SoC, in this case Kepler.  Also, it’s the first one.  So, K1.

The processor of the Tegra K1 look very familiar and include four ARM Cortex-A15 “r3” cores and 2MB of L2 cache with a fifth A15 core used for lower power situations.  This 4+1 design is the same that was introduced with the Tegra 4 processor last year and allows NVIDIA to implement a style of “big.LITTLE” design that is unique.  Some slight modifications to the cores are included with Tegra K1 that improve performance and efficiency, but not by much – the main CPU is very similar to the Tegra 4.

NVIDIA also unveiled late last night that another version of the Tegra K1 that replaces the quad A15 cores with two of the company's custom designs Denver CPU cores.  Project Denver, announced in early 2011, is NVIDIA's attempt at building its own core design based on the ARMv8 64-bit ISA.  This puts this iteration of Tegra K1 on the same level as Apple's A7 and Qualcomm's Krait processors.  When these are finally available in the wild it will be incredibly intriguing to see how well NVIDIA's architects did in the first true CPU design from the GPU giant.

Continue reading about NVIDIA's new Tegra K1 SoC with Kepler-based graphics!

Coverage of CES 2014 is brought to you by AMD!

PC Perspective's CES 2014 coverage is sponsored by AMD.

Follow all of our coverage of the show at http://pcper.com/ces!

CES 2014: NVIDIA Announces Tegra K1 SoC with 192 Kepler CUDA Cores, Denver ARMv8 Option

Subject: Processors, Mobile | January 5, 2014 - 08:43 PM |
Tagged: tegra k1, tegra, SoC, nvidia, kepler, CES 2014, CES

Update: Check out our more in-depth analysis of the Tegra K1 processor from NVIDIA.

Today during its CES 2014 press conference, NVIDIA announced the Tegra K1 SoC as the successor to the Tegra 4 processor.  This new ARM-based part includes 192 Kepler-based CUDA cores, sharing the same GPU architecture as the current GeForce GTX 700-series discrete graphics cards. 

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NVIDIA also announced the Epic has Unreal Engine 4 up and running on the Tegra K1, bringing an entirely new class of games to mobile Android devices.  We got to see some demonstrations from NVIDIA running on the K1 and I must admit the visuals were stunning.  Frame rates did get a bit choppy during the subway demo of UE4 but it's still early.

As an added surprise, NVIDIA is announcing a version of Tegra K1 that ships with the same quad-core A15 (4+1) design as the Tegra 4 BUT ALSO have a version that uses two NVIDIA Denver CPU cores!!  Denver is NVIDIA's custom CPU design based on the ARMv8 architecture, adding 64-bit support to another ARM partner's portfolio.

denver3.jpg

Tegra K1 is offered in two pin-to-pin compatible versions - a 32-bit quad-core (4-Plus-1 ARM Cortex-A15 CPU) and a custom, NVIDIA-designed 64-bit dual Super Core CPU. This CPU (codenamed “Project Denver”) delivers very high single-thread and multi-thread performance. Both versions deliver stunning graphics and visual computing capabilities powered by the 192-core NVIDIA Kepler GPU. 

NVIDIA has only had Denver back for a few days from the fab but there able to showcase it running Android.  It's been a long time since the initial announcement of this project and its great to finally see a result.

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Tegra K1 with quad-core A15 processor

We'll have an in-depth story on the Tegra K1 on Monday morning, 6am PST right here on PC Perspective so check back then!!

Coverage of CES 2014 is brought to you by AMD!

PC Perspective's CES 2014 coverage is sponsored by AMD.

Follow all of our coverage of the show at http://pcper.com/ces!

Intel is stacking memory on top of the new Xeons

Subject: General Tech | November 22, 2013 - 09:29 AM |
Tagged: Supercomputing Conference, Intel, SoC, Near Memory, knights landing

Intel spilled more beans about the new Near Memory architecture that will be accompanying their new Xeon release.  The memory will be stacked directly onto the CPU giving much quicker access than you would normally see from DDR3 which has to travel over the motherboard.  They have not disclosed expected speeds, which could be up to what we see in current CPU caches only in much larger sizes.  This is not quite a Xeon SoC but in the presentation The Register heard of Intel's plans to incorporate optical fabrics and switches onto the CPUs as well with size being the only limit.  Perhaps they do have a leg to stand on when they claim the return to power of homogeneous computing.

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"According to an EE Times report, Intel's Rajeeb Hazra, a VP and general manager of its data centre group, said Intel would customise high-end Xeon processors and Xeon Phi co-processors by closely integrating memory, both by adding memory dies to a processor package and, at a later date, integrating layers of memory dies into the processor along with optical fabrics and switches."

Here is some more Tech News from around the web:

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Source: The Register

Imagination Technologies Unleashes Warrior MIPS P5600 CPU Core Aimed at Embedded and Mobile Devices

Subject: Editorial, General Tech, Networking, Processors, Mobile | October 18, 2013 - 10:45 PM |
Tagged: SoC, p5600, MIPS, imagination

Imagination Technologies, a company known for its PowerVR graphics IP, has unleashed its first Warrior P-series MIPS CPU core. The new MIPS core is called the P5600 and is a 32-bit core based on the MIPS Release 5 ISA (Instruction Set Architecture).

The P5600 CPU core can perform 128-bit SIMD computations, provide hardware accelerated virtualization, and access up to a 1TB of memory via virtual addressing. While the MIPS 5 ISA provides for 64-bit calculations, the P5600 core is 32-bit only and does not include the extra 64-bit portions of the ISA.

Imagination Technologies Warrior MIPS P5600 CPU Core.png

The MIPS P5600 core can scale up to 2GHz in clockspeed when used in chips built on TSMC's 28nm HPM manufacturing process (according to Imagination Technologies). Further, the Warrior P5600  core can be used in processors and SoCs. As many as six CPU cores can be combined and managed by a coherence manager and given access to up to 8MB of shared L2 cache. Imagination Technologies is aiming processors containing the P5600 cores at mobile devices, networking appliances (routers, hardware firewalls, switches, et al), and micro-servers.

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A configuration of multiple P5600 cores with L2 cache.

I first saw a story on the P5600 over at the Tech Report, and found it interesting that Imagination Technologies was developing a MIPS processor aimed at mobile devices. It does make sense to see a MIPS CPU from the company as it owns the MIPS intellectual property. Also, a CPU core is a logical step for a company with a large graphics IP and GPU portfolio. Developing its own MIPS CPU core would allow it to put together an SoC with its own CPU and GPU components. With that said, I found it interesting that the P5600 CPU core was being aimed at the mobile space, where ARM processors currently dominate. ARM is working to increase performance while Intel is working to bring its powerhouse x86 architecture to the ultra low power mobile space. Needless to say, it is a highly competitive market and Imagination Technologies new CPU core is sure to have a difficult time establishing itself in that space of consumer smartphone and tablet SoCs. Fortunately, mobile chips are not the only processors Imagination Technologies is aiming the P5600 at. It is also offering up the MIPS Series 5 compatible core for use in processors powering networking equipment and very low power servers and business appliances where the MIPS architecture is more commonplace.

In any event, I'm interested to see what else IT has in store for its MIPS IP and where the Warrior series goes from here!

More information on the MIPS 5600 core can be found here.

Move over Intel, AMD has an announcement too

Subject: General Tech | September 10, 2013 - 01:10 PM |
Tagged: Steppe Eagle, SoC, Hierofalcon, GCN, Bald Eagle, amd, Adelaar

AMD have announced their new mobile roadmap and have changed their naming scheme drastically for these new processors.  The first of their ARM based processors will be called Hierofalcon and feature up to eight Cortex A57 processors capable of hitting 2GHz with a pair of 64-bit ECC DDR3 or DDR4 memory channels.  It will be a true SoC and feature both network and PCIe controllers as well as support for ARM's TrustZone.  Bald Eagle will have Steamroller cores and will be low TDP processors with a maximum of 35W and allow you to configure the maximum TDP to even lower levels if you so wish.  The final announcement dealt with the new GCN-based embedded series of GPUs called Adelaar which arrive in three different packages, a multi-chip module, a mobile PCIe module and a discrete GPU.  You can glean a bit more about these new families at DigiTimes.  

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"AMD has disclosed its roadmap for the embedded computing market, as it becomes the first company to offer both ARM and x86 processor solutions for low-power and high-performance embedded compute designs. The new lineup includes two x86 accelerated processing units (APUs) and CPUs, a high-performance ARM system-on-chip (SoC) and a new family of discrete AMD Embedded Radeon graphics processing units (GPUs) expected to launch in 2014."

Here is some more Tech News from around the web:

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Source: DigiTimes

Microsoft Shows Off Xbox One SoC At Hot Chips 25

Subject: General Tech | August 29, 2013 - 08:22 PM |
Tagged: xbox one, SoC, microsoft, gaming, console, amd

At the Hot Chips conference earlier this week, Microsoft showed off several slides detailing the SoC used in its upcoming Xbox One gaming console.

The Xbox One uses a System on a Chip (SoC) designed by AMD’s Semi-Custom Business Unit. The processor features eight “Jaguar” AMD CPU cores, an AMD GCN (Graphics Core Next) based GPU with 768 shader cores, an audio co-processor, and 32MB of on-chip eSRAM.

The SoC, measuring 363mm^2 is manufactured on TSMC’s 28nm HPM process. The chip can interface with 8GB of DDR3 main memory with bandwidth of 68.3 GB/s or utilize the on-chip SRAM which has bandwidth of 102GB/s. The embedded SRAM is in addition to the smaller L1 and L2 caches. The slides indicate that the GPU and CPU can at least access the SRAM, though it still remains frustratingly unknown if the SoC supports anything like AMD’s hUMA technology which would allow the CPU and GPU to both read and write to the same memory address spaces without having to copy data between CPU and GPU-accessible memory space. It may be that the CPU and GPU can use the SRAM, but the same memory spaces can not be shared, though that may be the pessimist in me talking. On the other hand, there could be something more, but it’s impossible to say from the block diagram spotted by Semi-Accurate at the Microsoft presentation.

Microsoft Xbox One Gaming Console.png

With that said, the slides do reveal a few interesting figures about the SoC that were not known previously. The Xbox One SoC has 47MB of on-chip memory including 32MB eSRAM used by the CPU and GPU and 64KB of SRAM used by the audio co-processor. The chip’s GPU is rated for Microsoft’s DirectX 11.1 and above graphics API. Further, Microsoft rates the GPU at 1.31 TFLOPS, 41 Gigatexels-per-second, and 13.6 Gigapixels-per-second. Additionally, the GCN-based GPU is able to hardware-encode multi-stream H.264 AVC MVC video and hardware decode multiple formats, including H.264 MVC. The hardware encoder is likely being used for the console’s game capture functionality.

The audio processors in the Xbox One SoC use two 128-bit SIMD floating point vector cores rated at 15.4 GFLOPS and “specialized hardware engines” and “signal processing optimized vector and scalar cores.”

The final interesting specification I got from the slides was that the SoC is able to go into a low power state that is as low as 2.5% of the chip’s full power using power islands and clock gating techniques.

You can find all of the geeky details in these slides over at SemiAccurate.

Source: SemiAccurate