Subject: Storage | February 14, 2016 - 02:51 PM | Allyn Malventano
Tagged: vnand, ssd, Samsung, nand, micron, Intel, imft, 768Gb, 512GB, 3d nand, 384Gb, 32 Layer, 256GB
You may have seen a wave of Micron 3D NAND news posts these past few days, and while many are repeating the 11-month old news with talks of 10TB/3.5TB on a 2.5"/M.2 form factor SSDs, I'm here to dive into the bigger implications of what the upcoming (and future) generation of Intel / Micron flash will mean for SSD performance and pricing.
Remember that with the way these capacity increases are going, the only way to get a high performance and high capacity SSD on-the-cheap in the future will be to actually get those higher capacity models. With such a large per-die capacity, smaller SSDs (like 128GB / 256GB) will suffer significantly slower write speeds. Taking this upcoming Micron flash as an example, a 128GB SSD will contain only four flash memory dies, and as I wrote about back in 2014, such an SSD would likely see HDD-level sequential write speeds of 160MB/sec. Other SSD manufacturers already recognize this issue and are taking steps to correct it. At Storage Visions 2016, Samsung briefed me on the upcoming SSD 750 Series that will use planar 16nm NAND to produce 120GB and 250GB capacities. The smaller die capacities of these models will enable respectable write performance and will also enable them to discontinue their 120GB 850 EVO as they transition that line to higher capacity 48-layer VNAND. Getting back to this Micron announcement, we have some new info that bears analysis, and that pertains to the now announced page and block size:
256Gb MLC: 16KB Page / 16MB Block / 1024 Pages per Block
384Gb TLC: 16KB Page / 24MB Block / 1536 Pages per Block
To understand what these numbers mean, using the MLC line above, imagine a 16MB CD-RW (Block) that can write 1024 individual 16KB 'sessions' (Page). Each 16KB can be added individually over time, and just like how files on a CD-RW could be modified by writing a new copy in the remaining space, flash can do so by writing a new Page and ignoring the out of date copy. Where the rub comes in is when that CD-RW (Block) is completely full. The process at this point is very similar actually, in that the Block must be completely emptied before the erase command (which wipes the entire Block) is issued. The data has to go somewhere, which typically means writing to empty blocks elsewhere on the SSD (and in worst case scenarios, those too may need clearing before that is possible), and this moving and erasing takes time for the die to accomplish. Just like how wiping a CD-RW took a much longer than writing a single file to it, erasing a Block takes typically 3-4x as much time as it does to program a page.
With that explained, of significance here are the growing page and block sizes in this higher capacity flash. Modern OS file systems have a minimum bulk access size of 4KB, and Windows versions since Vista align their partitions by rounding up to the next 2MB increment from the start of the disk. These changes are what enabled HDDs to transition to Advanced Format, which made data storage more efficient by bringing the increment up from the 512 Byte sector up to 4KB. While most storage devices still use 512B addressing, it is assumed that 4KB should be the minimum random access seen most of the time. Wrapping this all together, the Page size (minimum read or write) is 16KB for this new flash, and that is 4x the accepted 4KB minimum OS transfer size. This means that power users heavy on their page file, or running VMs, or any other random-write-heavy operations being performed over time will have a more amplified effect of wear of this flash. That additional shuffling of data that must take place for each 4KB write translates to lower host random write speeds when compared to lower capacity flash that has smaller Page sizes closer to that 4KB figure.
A rendition of 3D IMFT Floating Gate flash, with inset pulling back some of the tunnel oxide layer to show the location of the floating gate. Pic courtesy Schiltron.
Fortunately for Micron, their choice to carry Floating Gate technology into their 3D flash has netted them some impressive endurance benefits over competing Charge Trap Flash. One such benefit is a claimed 30,000 P/E (Program / Erase) cycle endurance rating. Planar NAND had dropped to the 3,000 range at its lowest shrinks, mainly because there was such a small channel which could only store so few electrons, amplifying the (negative) effects of electron leakage. Even back in the 50nm days, MLC ran at ~10,000 cycle endurance, so 30,000 is no small feat here. The key is that by using that same Floating Gate tech so good at controlling leakage for planar NAND on a new 3D channel that can store way more electrons enables excellent endurance that may actually exceed Samsung's Charge Trap Flash equipped 3D VNAND. This should effectively negate the endurance hit on the larger Page sizes discussed above, but the potential small random write performance hit still stands, with a possible remedy being to crank up the Over-Provisioning of SSDs (AKA throwing flash at the problem). Higher OP means less active pages per block and a reduction in the data shuffling forced by smaller writes.
A 25nm flash memory die. Note the support logic (CMOS) along the upper left edge.
One final thing helping out Micron here is that their Floating Gate design also enables a shift of 75% of the CMOS circuitry to a layer *underneath* the flash storage array. This logic is typically part of what you see 'off to the side' of a flash memory die. Layering CMOS logic in such a way is likely thanks to Intel's partnership and CPU development knowledge. Moving this support circuitry to the bottom layer of the die makes for less area per die dedicated to non-storage, more dies per wafer, and ultimately lower cost per chip/GB.
Samsung's Charge Trap Flash, shown in both planar and 3D VNAND forms.
One final thing before we go. If we know anything about how the Intel / Micron duo function, it is that once they get that freight train rolling, it leads to relatively rapid advances. In this case, the changeover to 3D has taken them a while to perfect, but once production gains steam, we can expect to see some *big* advances. Since Samsung launched their 3D VNAND their gains have been mostly iterative in nature (24, 32, and most recently 48). I'm not yet at liberty to say how the second generation of IMFT 3D NAND will achieve it, but I can say that it appears the next iteration after this 32-layer 256Gb (MLC) /384Gb (TLC) per die will *double* to 512Gb/768Gb (you are free to do the math on what that means for layer count). Remember back in the day where Intel launched new SSDs at a fraction of the cost/GB of the previous generation? That might just be happening again within the next year or two.
Subject: General Tech | February 4, 2016 - 11:53 AM | Ken Addison
Tagged: video, Trion 150, tesla, steam os, Samsung, rise of the tomb raider, podcast, ocz, NVMe, Jim Keller, amd, 950 PRO
PC Perspective Podcast #385 - 02/04/2016
Join us this week as we discuss Rise of the Tomb Raider performance, a triple RAID-0 NVMe array and more!
The URL for the podcast is: http://pcper.com/podcast - Share with your friends!
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Hosts: Ryan Shrout, Jeremy Hellstrom, Josh Walrath, and Allyn Malventano
Program length: 1:16:38
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- Week in Review:
- 0:44:25 Winner: EVGA Winter 2016 Prize Pack and Giveaway
- News items of interest:
- 0:46:35 Gigabyte adds full GIMPS and Prime95 compatibility to Skylake processors
- 0:48:40 So That's Where Jim Keller Went To... Tesla Motors…
- 0:54:40 AMD FirePro S-Series Introduces Hardware-Based GPU Virtualization
- 0:56:15 Who's a pretty boy? Is it you Fallout?
- 0:58:40 OCZ Launches Trion 150, Successor to Trion 100 SATA SSD, Using 15nm Flash
- Hardware/Software Picks of the Week:
- http://twitter.com/ryanshrout and http://twitter.com/pcper
NVMe was a great thing to happen to SSDs. The per-IO reduction in latency and CPU overhead was more than welcome, as PCIe SSDs were previously using the antiquated AHCI protocol, which was a carryover from the SATA HDD days. With NVMe came additional required support in Operating Systems and UEFI BIOS implementations. We did some crazy experiments with arrays of these new devices, but we were initially limited by the lack of native hardware-level RAID support to tie multiple PCIe devices together. The launch of the Z170 chipset saw a remedy to this, by including the ability to tie as many as three PCIe SSDs behind a chipset-configured array. The recent C600 server chipset also saw the addition of RSTe capability, expanding this functionality to enterprise devices like the Intel SSD P3608, which was actually a pair of SSDs on a single PCB.
Most Z170 motherboards have come with one or two M.2 slots, meaning that enthusiasts wanting to employ the 3x PCIe RAID made possible by this new chipset would have to get creative with the use of interposer / adapter boards (or use a combination of PCI and U.2 connected Intel SSD 750s). With the Samsung 950 Pro available, as well as the slew of other M.2 SSDs we saw at CES 2016, it’s safe to say that U.2 is going to push back into the enterprise sector, leaving M.2 as the choice for consumer motherboards moving forward. It was therefore only a matter of time before a triple-M.2 motherboard was launched, and that just recently happened - Behold the Gigabyte Z170X-SOC Force!
This new motherboard sits at the high end of Gigabyte’s lineup, with a water-capable VRM cooler and other premium features. We will be passing this board onto Morry for a full review, but this piece will be focusing on one section in particular:
I have to hand it to Gigabyte for this functional and elegant design choice. The space between the required four full length PCIe slots makes it look like it was chosen to fit M.2 SSDs in-between them. I should also note that it would be possible to use three U.2 adapters linked to three U.2 Intel SSD 750s, but native M.2 devices makes for a significantly more compact and consumer friendly package.
With the test system set up, let’s get right into it, shall we?
Subject: Graphics Cards, Memory | January 19, 2016 - 11:01 PM | Scott Michaud
Tagged: Samsung, HBM2, hbm
Samsung has just announced that they have begun mass production of 4GB HBM2 memory modules. When used on GPUs, four packages can provide 16GB of Video RAM with very high performance. They do this with a very wide data bus, which trade off frequency for transferring huge chunks. Samsung's offering is rated at 256 GB/s per package, which is twice what the Fury X could do with HBM1.
They also expect to mass produce 8GB HBM2 packages within this calendar year. I'm guessing that this means we'll see 32GB GPUs in the late-2016 or early-2017 time frame unless "within this year" means very, very soon (versus Q3/Q4). They will likely be for workstation or professional cards, but, in NVIDIA's case, those are usually based on architectures that are marketed to high-end gaming enthusiasts through some Titan offering. There's a lot of ways this could go, but a 32GB Titan seems like a bit much; I wouldn't expect that this affects the enthusiast gamer segment. It might mean that professionals looking to upgrade from the Kepler-based Tesla K-series might be waiting a little longer, maybe even GTC 2017. Alternatively, they might get new cards, just with a 16GB maximum until a refresh next year. There's not enough information to know one way or the other, but it's something to think about when more of it starts rolling in.
Samsung's HBM2 are compatible with ECC, although I believe that was also true for at least some HBM1 modules from SK Hynix.
Subject: Storage, Shows and Expos | January 6, 2016 - 12:15 AM | Allyn Malventano
Tagged: T3, ssd, Samsung, portable, msata, CES 2016, CES, 850 EVO
We got our first look at the Samsung T1 SSD at CES 2015. The concept was simple - Make a very compact external portable encrypted drive, and make it fast. Based on a 3D VNAND equipped mSATA 850 EVO and using an ASMedia USB to SATA bridge, the T1 had no issue saturating the SATA side of the link and was capable of well over 400 MB/s over a USB 3.0 link.
This year Samsung is teasing the next iteration on this product:
Dubbed the T3 (T2 doesn't translate well in some other languages), the T3 has some notable changes / updates / upgrades over the T1 of last year:
- Type-C connector on the device end of the cable (we assume the included cable will link to Standard A for compatibility). The T1 used micro-B.
- Metal case / housing. T1 was all plastic.
- Capacities up to 2TB. T1 was limited to 1TB.
Full press blast / additional details / specs appear after the break. Look out for a review of this one just as soon as we can get our hands on one!
*Update* I got my hands on one at a Samsung press dinner. Here it is next to the older T1. The T3 is a tiny bit larger and thicker, but the difference is hardly noticeable as the T1 was very thin and light as it was. Here's a pic:
Follow all of our coverage of the show at http://pcper.com/ces!
Subject: Storage, Shows and Expos | January 5, 2016 - 01:39 AM | Allyn Malventano
Tagged: CES, CES 2016, Fasetto, Link, wifi, NAS, ssd, Samsung, vnand, 802.11ac
Fasetto is a company previously known as one of those cross-platform file-sharing web apps, but I was shocked to see them with a space at CES Unveiled. Companies without physical products tend to fall flat at this type of venue, but as I walked past, boy was I mistaken!
To give the size a bit of perspective here, that's a business card sitting in front of the 'Link', which only measures 1.9x1.9x0.9" and weighs just under 4 ounces. That's a belt clip to the right of it. Ok, now that we have the tiny size and low weight described, what has Fasetto packed into that space?
- Aluminum + ABS construction
- Waterproof to 45 feet (and it floats!)
- Bluetooth 4.0 LE
- 802.11AC dual band WiFi (reportedly 4x4)
- 4GB RAM
- Quad core ARM CPU
- 9-axis compass/accelerometer/gyro
- 1350 mAh Li battery
- Wireless charging (Chi style)
- Up to 2TB SSD
For a portable storage device, that is just an absolutely outstanding spec sheet! The Link is going to run an OS designed specifically for this device, and will have plugin support (simple add-on apps that can access the accelerometer and log movement, for example).
The BIG deal with this device is of course the ability to act as a portable wireless storage device. In that respect it can handle 20 simultaneous devices, stream to seven simultaneously, and can also do the expected functions like wireless internet pass-through. Claimed standby power is two weeks and active streaming is rated at up to 8 hours. Even more interesting is that I was told the internal storage will be Samsung 48-layer VNAND borrowed from their T3 (which explains why the Fasetto Link will not be available until late 2016). This is sure to be a hit with photographers, as WiFi compatible cameras should be able to stream photos to the Link as the photos are being taken, eliminating the need to offload cameras at the end of a shoot.
We will definitely be working with Fasetto to help shake out any bugs prior to the release of this little gem. I suspect it might just be the most groundbreaking storage product that we see come out of this CES.
Follow all of our coverage of the show at http://pcper.com/ces!
Subject: General Tech | December 22, 2015 - 02:07 PM | Jeremy Hellstrom
Tagged: amd, Samsung, 14nm, rumour
The talk around the watercooler includes a rumour that AMD may use Samsung to produce at least some of their 14nm chips in the coming year. If true this has been a huge year for Samsung who produce NVIDIA chips as well as recently picking up a contract with Apple to produce some of their A9 SoCs. The rumour still includes GLOBALFOUNDRIES as a source for APUs and GPUs so this would make Samsung a second source for working silicon, which we can hope will alleviate some of AMD's difficulty in maintaining supplies of products. This could also help fund Samsung's development of their 10nm FinFET node which the claim should be in production by the end of 2016. As always, take the rumour for what it is but if you want to learn more about what is being said you can pop over to The Inquirer.
"A report in South Korea's Electronic Times, which cited unknown sources, said that Samsung Electronics will start making new chips for AMD sometime next year."
Here is some more Tech News from around the web:
- Toshiba denies NAND exit report with 'no decision made' comment @The Register
- 25 years ago: Sir Tim Berners-Lee builds world's first website @ The Register
- Facepalm time: Windows 10 security patch wipes custom Word autotext @ The Register
- Make Show-Stopping Netflix Socks @ MAKE:Blog
Subject: Mobile | November 28, 2015 - 09:05 PM | Scott Michaud
Tagged: Samsung, s7, galaxy
The follow-up to the Samsung Galaxy S6 is already being rumored, which people are obviously calling the Galaxy S7. The last two phones were unveiled at Mobile World Congress in Barcelona, Spain, which takes place in late February / early March. Information coming out in November is a bit... early. Some sites believe that Samsung will announce the phone in January, but who knows? Some of the rumors are interesting, though.
The one that catches my attention is the potential inclusion of a microSD card slot. External storage is rare these days, with Google removing it from their Nexus line and severely limiting what apps can do with the contents. That said, Android 6.0, recently released for a few devices, made further changes to increase its capabilities. You can now use SD cards as internal storage, but only if you agree to format and encrypt the storage to use only on that device. While the recent batch of Nexus phones don't include a microSD card slot, the changes might be enough to sway third-party manufacturers to include a slot.
As a developer, it would certainly be nice, especially if you intend to develop software that uses an SD card. Makes sense, right? Purchasing a developer phone that has all the features you might want to target?
Speaking of developer phones, the upcoming device should have a top-of-the-line processor in it. Reports are split between the Snapdragon 820 and the Exynos 8890. If it's the latter, availability is expected Q1 2016; the former started sampling a few months ago and was launched on November 11th. As such, SoC availability should be ready if Samsung intends to launch the phone early, regardless of the chosen chip, but that's probably not the limiting factor. It is also entirely possible that Samsung could include different processors for different markets. Qualcomm was absent from the Galaxy S6 line, but the S5 had some sub-models using Qualcomm processors and others Samsung's own implementation.
Either way, they are fast processors that support OpenGL ES 3.1 + AEP at the very least. The Adreno 530 is rated for about 550 GFLOPs, which is a tiny bit faster than a GeForce 9800 GT, although with Vulkan-level feature support (provided correct drivers). Thankfully Google has been more friendly to Khronos-based standards, and Samsung even more so.
When will we know for sure? Don't know. How much will it cost? Don't know. What will it be officially called? Don't know, but anything other than Galaxy S7 would be surprising. Would it make sense for Samsung to shake up the date and other long-running details? Well, the Galaxy S6 launch was lackluster, so this would be the most likely time for them to be squirrely. We'll see.
Subject: Memory | November 26, 2015 - 05:23 PM | Scott Michaud
Tagged: TSV, Samsung, enterprise, ddr4
You may remember Allyn's article about TSV memory back from IDF 2014. Through this process, Samsung and others are able to stack dies of memory onto a single package, which can increase density and bandwidth. This is done by punching holes through the dies and connecting them down to the PCB. The first analogy that comes to mind is an elevator shaft, but I'm not sure how accurate that is.
Anyway, Samsung has been applying it to enterprise-class DDR4 memory, which leads to impressive capacities. 64GB sticks, individual sticks, were introduced in 2014. This year, that capacity doubles to 128GB. The chips are fabricated at 20nm and each contain 8Gb (1GB) per layer. Each stick contains 36 packages of four chips.
At the end of their press release, Samsung also mentioned that they intend to expand their TSV technology into “HBM and consumer products.”
Subject: Processors, Mobile | November 12, 2015 - 09:30 AM | Sebastian Peak
Tagged: SoC, smartphone, Samsung Galaxy, Samsung, mobile, Exynos 8890, Exynos 8 Octa, Exynos 7420, Application Processor
Coming just a day after Qualcomm officially launched their Snapdragon 820 SoC, Samsung is today unveiling their latest flagship mobile part, the Exynos 8 Octa 8890.
The Exynos 8 Octa 8890 is built on Samsung’s 14 nm FinFET process like the previous Exynos 7 Octa 7420, and again is based on the a big.LITTLE configuration; though the big processing cores are a custom design this time around. The Exynos 7420 was comprised of four ARM Cortex A57 cores and four small Cortex A53 cores, and while the small cores in the 8890 are again ARM Cortex A53, the big cores feature Samsung’s “first custom designed CPU based on 64-bit ARMv8 architecture”.
“With Samsung’s own SCI (Samsung Coherent Interconnect) technology, which provides cache-coherency between big and small cores, the Exynos 8 Octa fully utilizes benefits of big.LITTLE structure for efficient usage of the eight cores. Additionally, Exynos 8 Octa is built on highly praised 14nm FinFET process. These all efforts for Exynos 8 Octa provide 30% more superb performance and 10% more power efficiency.”
Another big advancement for the Exynos 8 Octa is the integrated modem, which provides Category 12/13 LTE with download speeds (with carrier aggregation) of up to 600 Mbps, and uploads up to 150 Mbps. This might sound familiar, as it mirrors the LTE Release 12 specs of the new modem in the Snapdragon 820.
Video processing is handled by the Mali-T880 GPU, moving up from the Mali-T760 found in the Exynos 7 Octa. The T880 is “the highest performance and the most energy-efficient mobile GPU in the Mali family”, with up to 1.8x the performance of the T760 while being 40% more energy-efficient.
Samsung will be taking this new SoC into mass production later this year, and the chip is expected to be featured in the company’s upcoming flagship Galaxy phone.
Full PR after the break.