Everything old is new again on the Internet o' Thangs

Subject: General Tech | July 7, 2014 - 02:34 PM |
Tagged: internet of things, MIPS, prpl, linaro

Imagination Technologies is reinvigorating their MIPS architecture by collaborating with Oracle and Qualcomm on MIPS-focused Java and OpenWRT Linux as well as continuing older partnerships with Ingenic and Ineda Systems.  MIPS has been a large player in low power WiFi enabled SoC's for quite a while with three billion MIPS-based products shipped in set-top boxes, mobile phones and wearable tech but have seen ARM take the lead and continue to garner more market share along with Intel's Quark.  These new partnerships may help MIPS based devices become more popular as some of the projects being developed are quite interesting, for instance Linux.com mentions the Dhanush Wearable Processing Unit which will run Linux and is aiming for a battery life of 30 days.

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"Imagination Technologies has launched a campaign to turn the 30-year-old MIPS architecture into an Internet of Things platform.

The IP designer's recent moves include the establishment of a Linaro-like "Prpl" industry group for MIPS, as well as collaborations with Oracle and Qualcomm on MIPS-focused Java and OpenWRT Linux development, respectively."

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Source: Linux.com

Imagination Technologies Unleashes Warrior MIPS P5600 CPU Core Aimed at Embedded and Mobile Devices

Subject: Editorial, General Tech, Networking, Processors, Mobile | October 19, 2013 - 01:45 AM |
Tagged: SoC, p5600, MIPS, imagination

Imagination Technologies, a company known for its PowerVR graphics IP, has unleashed its first Warrior P-series MIPS CPU core. The new MIPS core is called the P5600 and is a 32-bit core based on the MIPS Release 5 ISA (Instruction Set Architecture).

The P5600 CPU core can perform 128-bit SIMD computations, provide hardware accelerated virtualization, and access up to a 1TB of memory via virtual addressing. While the MIPS 5 ISA provides for 64-bit calculations, the P5600 core is 32-bit only and does not include the extra 64-bit portions of the ISA.

Imagination Technologies Warrior MIPS P5600 CPU Core.png

The MIPS P5600 core can scale up to 2GHz in clockspeed when used in chips built on TSMC's 28nm HPM manufacturing process (according to Imagination Technologies). Further, the Warrior P5600  core can be used in processors and SoCs. As many as six CPU cores can be combined and managed by a coherence manager and given access to up to 8MB of shared L2 cache. Imagination Technologies is aiming processors containing the P5600 cores at mobile devices, networking appliances (routers, hardware firewalls, switches, et al), and micro-servers.

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A configuration of multiple P5600 cores with L2 cache.

I first saw a story on the P5600 over at the Tech Report, and found it interesting that Imagination Technologies was developing a MIPS processor aimed at mobile devices. It does make sense to see a MIPS CPU from the company as it owns the MIPS intellectual property. Also, a CPU core is a logical step for a company with a large graphics IP and GPU portfolio. Developing its own MIPS CPU core would allow it to put together an SoC with its own CPU and GPU components. With that said, I found it interesting that the P5600 CPU core was being aimed at the mobile space, where ARM processors currently dominate. ARM is working to increase performance while Intel is working to bring its powerhouse x86 architecture to the ultra low power mobile space. Needless to say, it is a highly competitive market and Imagination Technologies new CPU core is sure to have a difficult time establishing itself in that space of consumer smartphone and tablet SoCs. Fortunately, mobile chips are not the only processors Imagination Technologies is aiming the P5600 at. It is also offering up the MIPS Series 5 compatible core for use in processors powering networking equipment and very low power servers and business appliances where the MIPS architecture is more commonplace.

In any event, I'm interested to see what else IT has in store for its MIPS IP and where the Warrior series goes from here!

More information on the MIPS 5600 core can be found here.

AMD Hires Veteran CPU Architect in Jim Keller

Subject: Processors | August 1, 2012 - 08:38 AM |
Tagged: x86-64, x86, MIPS, Jim Keller, arm, amd, Alpha

There has been quite a bit of news lately from AMD, and very little of it good.  What has perhaps dominated the headlines throughout this past year was the amount of veteran AMD employees who have decided (or were pushed) to seek employment elsewhere.  Not much has been said from these departing employees, but Rory Read certainly started things off with a bang by laying off some 10% of the company just months into his tenure.

Now we finally have some good news in terms of employment.  AMD has hired a pretty big name in the industry.  Not just a big name, but a person who was one of the primary leads on two of AMD’s most successful architectures to date.  Jim Keller is coming back to AMD, and at a time where it seems AMD needs some veteran leadership who is very in touch with not just the industry, but CPU architecture design.

Jim was a veteran of DEC and worked on some of the fastest Alpha processors of the time.  Much could be written about DEC and how they let what could have been one of the most important and profitable architectures in computing history sit essentially on the back burner while they focused on seemingly dinosaur age computing.  After the Alpha was sold off and DEC sold away, Jim found his way to AMD and played a very important role at that company.

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The first product was helping to launch the K7, and worked primarily with system engineering.  The vast majority of design work for the K7 was finished by the time he signed on, but he apparently worked quite a bit on integrating it into the new socket architecture that was derived from the DEC Alpha.  Where Jim really earned his keep was in co-authoring the x86-64 specification and being lead architect on the AMD K8 series of processors.  While he left in 1999, the mark he left on AMD is essentially indelible.

After AMD he joined Sibyte (Broadcom) and was lead architect on a series of MIPS processors used in networking devices.  This lasted until 2003 and he again left the company seemingly more prosperous than when he began.

PA-Semi was the next stop and he worked again primarily on networking specific SOCs utilizing the PowerPC architecture.  So far, by counting fingers, Jim has worked on five major ISAs (Alpha, x86, x86-64, MIPS, and PowerPC).  These chips were able to power networking devices with 10 Gb throughput.  PA-Semi was then purchased by Apple in 2007/2008.

At Apple Jim was now Director of Platform Architecture and worked with yet another major ISA; ARM.  Jim worked to develop several major and successful products with the A4 and A5 processors that have powered the latest iPhone and iPad products from the Cupertino giant.  To say that this individual has had his fingers in some very important pies is an understatement.

Jim now rejoins AMD as CVP and Chief Architect of CPU Cores.  He will report directly to Mark Papermaster.  His primary job is to improve execution efficiency and consistency, as well as implement next generation features into future CPU cores which will keep AMD competitive with not only Intel, but other rising competitors in the low power space.  This is finally some good news for AMD as they are actually adding talent rather than losing it.  While Jim may not be able to turn the company around overnight, he does look to be an important piece of the puzzle with a huge amount of experience and knowhow with multiple CPU ISA.  If there is anyone that can tackle the challenges in front of AMD in the face of a changing world, this might be the guy.  So far he has had a positive impact in every stop he has made, and perhaps this could prove to be the pinnacle of his career.  Or it could be where his career goes to die.  It is hard to say, but I do think that AMD made a good hire with Jim.

Source: AMD

Intel watches sadly from a window as HP goes out ARM in ARM with Caxeda

Subject: General Tech | October 27, 2011 - 12:44 PM |
Tagged: arm, hp, servers, Calexda, MIPS, Godson

There have been many discussions as of late on the eventual arrival of ARM in the server room, with AMD and Intel suffering the losses.  A company called Calexda has made the possibility into reality with their own custom designed ARM chips. They figure on cramming 120 of the processors into a 2U box with incredibly low power draw; in the neighbourhood of a 90% reduction.  AMD's customers may stay with an architecture that they know, however Intel stands to lose power conscious customers if Calexda can provide performance and compatibility.  SemiAccurate also touches on Lenovo's investigation of building servers based on a MIPS design called Godson.

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"According to a report from Bloomberg News Service HP (NYSE:HPQ) will start manufacturing servers based on the ARM architecture in a sharp departure from its previous Intel-only design philosophy.

The processors for the HP servers will come from the startup Caxeda, which is partly owned by ARM. Caxeda is planning a quadcore processor based on the ARM Cortex-A9 design."

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Source: SemiAccurate