Intel Revises All SSD Product Lines - 3D NAND Everywhere!

Subject: Storage | August 25, 2016 - 06:26 PM |
Tagged: ssd, Pro 6000p, Intel, imft, E 6000p, E 5420s, DC S3520, DC P3520, 600p, 3d nand

Intel announced the production of 3D NAND a little over a year ago, and we've now seen production ramp up to the point where they are infusing it into nearly every nook and cranny of their SSD product lines.

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The most relevant part for our readers will be a long overdue M.2 2280 SSD. These will kick off with the 600p:

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An overseas forum member over at chiphell got their hands on a 600p and ran some quick tests. From their photo (above), we can confirm the controller is not from Intel, but rather from Silicon Motion. The NAND is naturally from Intel, as is likely their controller firmware implementation, as these parts go through the same lengthy validation process as their other products.

Intel is going for the budget consumer play here. The flash will be running in TLC mode, likely with an SLC cache. Specs are respectable - 1.8GB/s reads, 560MB/s writes, random read 155k, random write 128k (4KB QD=32). By respectable specs I mean in light of the pricing:

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Wow! These prices are ranging from $0.55/GB at 128GB all the way down to $0.35/GB for the 1TB part.

You might have noticed the Pro 6000p in that list. Those are nearly identical to the 600p save some additional firmware / software tweaks to support IT infrastructure remote secure erase.

Intel also refreshed their DataCenter (DC) lineup. The SSD DC S3520 (SATA) and P3520 (PCIe/NVMe) were also introduced as a refresh, also using Intel's 3D NAND. We published our exclusive review of the Intel SSD DC P3520 earlier today, so check there for full details on that enterprise front. Before we move on, a brief moment of silence for the P3320 - soft-launched in April, but discontinued before it shipped. We hardly knew ye.

Lastly, Intel introduced a few additional products meant for the embedded / IoT sector. The SSD E 6000p is an M.2 PCIe part similar to the first pair of products mentioned in this article, while the SSD E 5420s comes in 2.5" and M.2 SATA flavors. The differentiator on these 'E' parts is enhanced AES 256 crypto.

Most of these products will be available 'next week', but the 600p 360GB (to be added) and 1TB capacities will ship in Q4.

Abbreviated press blast appears after the break.

Source: Intel
Subject: Storage
Manufacturer: Intel

Introduction, Specifications and Packaging

Introduction:

Intel launched their Datacenter 'P' Series parts a little over two years ago. Since then, the P3500, P3600, and P3700 lines have seen various expansions and spinoffs. The most recent to date was the P3608, which packed two full P3600's into a single HHHL form factor. With Intel 3D XPoint / Optane parts lurking just around the corner, I had assumed there would be no further branches of the P3xxx line, but Intel had other things in mind. IMFT 3D NAND offers greater die capacities at a reduced cost/GB, apparently even in MLC form, and Intel has infused this flash into their new P3520:

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Remember the P3500 series was Intel's lowest end of the P line, and as far as performance goes, the P3520 actually takes a further step back. The play here is to get the proven quality control and reliability of Intel's datacenter parts into a lower cost product. While the P3500 launched at $1.50/GB, the P3520 pushes that cost down *well* below $1/GB for a 2TB HHHL or U.2 SSD.

Read on for our full review of the Intel DC P3520 SSD!

Love upgrading memory on your laptop? Double check any Apollo Lake machines you like.

Subject: General Tech | August 24, 2016 - 01:01 PM |
Tagged: ultraportable, LPDDR4, Intel, apollo lake

A report from DigiTimes is bad news for those who like to upgrade their ultraportable laptops.  To cut down on production costs companies like Acer, Lenovo, Asustek Computer, HP and Dell will use on-board memory as opposed to DIMMs on their Apollo Lake based machines.  This should help keep the costs of flipbooks, 2 in 1's and other small machines stable or even lower them by a small amount but does mean that they cannot easily be upgraded. Many larger notebooks will also switch to this style of memory so be sure to do your research before purchasing a new mobile system.

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"Notebook vendors have mostly adopted on-board memory designs in place of DIMMs to make their Intel Apollo Lake-based notebooks as slim as possible, according to sources from Taiwan's notebook supply chain"

Here is some more Tech News from around the web:

Tech Talk

Source: DigiTimes
Manufacturer: PC Perspective

Why Two 4GB GPUs Isn't Necessarily 8GB

We're trying something new here at PC Perspective. Some topics are fairly difficult to explain cleanly without accompanying images. We also like to go fairly deep into specific topics, so we're hoping that we can provide educational cartoons that explain these issues.

This pilot episode is about load-balancing and memory management in multi-GPU configurations. There seems to be a lot of confusion around what was (and was not) possible with DirectX 11 and OpenGL, and even more confusion about what DirectX 12, Mantle, and Vulkan allow developers to do. It highlights three different load-balancing algorithms, and even briefly mentions what LucidLogix was attempting to accomplish almost ten years ago.

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If you like it, and want to see more, please share and support us on Patreon. We're putting this out not knowing if it's popular enough to be sustainable. The best way to see more of this is to share!

Open the expanded article to see the transcript, below.

Intel's new SoC, the Joule

Subject: General Tech | August 18, 2016 - 02:20 PM |
Tagged: Intel, joule, iot, IDF 2016, SoC, 570x, 550x, Intel RealSense

Intel has announced the follow up to Edison and Curie, their current SoC device, called Joule.  They have moved away from the Quark processors they previously used to a current generation Atom.  The device is designed to compete against NVIDIA's Jetson as it is far more powerful than a Raspberry Pi and will be destined for different usage.  It will support Intel RealSense, perhaps appearing in the newly announced Project Alloy VR headset.  Drop by Hack a Day for more details on the two soon to be released models, the Joule 570x and 550x.

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"The high-end board in the lineup features a quad-core Intel Atom running at 2.4 GHz, 4GB of LPDDR4 RAM, 16GB of eMMC, 802.11ac, Bluetooth 4.1, USB 3.1, CSI and DSI interfaces, and multiple GPIO, I2C, and UART interfaces."

Here is some more Tech News from around the web:

Tech Talk

Source: Hack a Day

Podcast #413 - NVIDIA Pascal Mobile, ARM and Intel partner on 10nm, Flash Memory Summit and more!

Subject: Editorial | August 18, 2016 - 02:20 PM |
Tagged: video, podcast, pascal, nvidia, msi, mobile, Intel, idf, GTX 1080, gtx 1070, gtx 1060, gigabyte, FMS, Flash Memory Summit, asus, arm, 10nm

PC Perspective Podcast #413 - 08/18/2016

Join us this week as we discuss the new mobile GeForce GTX 10-series gaming notebooks, ARM and Intel partnering on 10nm, Flash Memory Summit and more!

You can subscribe to us through iTunes and you can still access it directly through the RSS page HERE.

The URL for the podcast is: http://pcper.com/podcast - Share with your friends!

Hosts:  Allyn Malventano, Sebastian Peak, Josh Walrath and Jeremy Hellstrom

Program length: 1:29:39
  1. Week in Review:
  2. This episode of PC Perspective is brought to you by Casper!! Use code “PCPER”
  3. News items of interest:
    1. 0:42:05 Final news from FMS 2016
  4. Hardware/Software Picks of the Week
    1. Ryan: VR Demi Moore
  5. Closing/outro

Intel Larrabee Post-Mortem by Tom Forsyth

Subject: Graphics Cards, Processors | August 17, 2016 - 01:38 PM |
Tagged: Xeon Phi, larrabee, Intel

Tom Forsyth, who is currently at Oculus, was once on the core Larrabee team at Intel. Just prior to Intel's IDF conference in San Francisco, which Ryan is at and covering as I type this, Tom wrote a blog post that outlined the project and its design goals, including why it didn't hit market as a graphics device. He even goes into the details of the graphics architecture, which was almost entirely in software apart from texture units and video out. For instance, Larrabee was running FreeBSD with a program, called DirectXGfx, that gave it the DirectX 11 feature set -- and it worked on hundreds of titles, too.

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Also, if you found the discussion interesting, then there is plenty of content from back in the day to browse. A good example is an Intel Developer Zone post from Michael Abrash that discussed software rasterization, doing so with several really interesting stories.

That old chestnut again? Intel compares their current gen hardware against older NVIDIA kit

Subject: General Tech | August 17, 2016 - 12:41 PM |
Tagged: nvidia, Intel, HPC, Xeon Phi, maxwell, pascal, dirty pool

There is a spat going on between Intel and NVIDIA over the slide below, as you can read about over at Ars Technica.  It seems that Intel have reached into the industries bag of dirty tricks and polished off an old standby, testing new hardware and software against older products from their competitors.  In this case it was high performance computing products which were tested, Intel's new Xeon Phi against NVIDIA's Maxwell, tested on an older version of the Caffe AlexNet benchmark.

NVIDIA points out that not only would they have done better than Intel if an up to date version of the benchmarking software was used, but that the comparison should have been against their current architecture, Pascal.  This is not quite as bad as putting undocumented flags into compilers to reduce the performance of competitors chips or predatory discount programs but it shows that the computer industry continues to have only a passing acquaintance with fair play and honest competition.

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"At this juncture I should point out that juicing benchmarks is, rather sadly, par for the course. Whenever a chip maker provides its own performance figures, they are almost always tailored to the strength of a specific chip—or alternatively, structured in such a way as to exacerbate the weakness of a competitor's product."

Here is some more Tech News from around the web:

Tech Talk

Source: Ars Technica
Author:
Subject: Editorial
Manufacturer: ARM

A Watershed Moment in Mobile

This previous May I was invited to Austin to be briefed on the latest core innovations from ARM and their partners.  We were introduced to new CPU and GPU cores, as well as the surrounding technologies that provide the basis of a modern SOC in the ARM family.  We also were treated to more information about the process technologies that ARM would embrace with their Artisan and POP programs.  ARM is certainly far more aggressive now in their designs and partnerships than they have been in the past, or at least they are more willing to openly talk about them to the press.

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The big process news that ARM was able to share at this time was the design of 10nm parts using an upcoming TSMC process node.  This was fairly big news as TSMC was still introducing parts on their latest 16nm FF+ line.  NVIDIA had not even released their first 16FF+ parts to the world in early May.  Apple had dual sourced their 14/16 nm parts from Samsung and TSMC respectively, but these were based on LPE and FF lines (early nodes not yet optimized to LPP/FF+).  So the news that TSMC would have a working 10nm process in 2017 was important to many people.  2016 might be a year with some good performance and efficiency jumps, but it seems that 2017 would provide another big leap forward after years of seeming stagnation of pure play foundry technology at 28nm.

Yesterday we received a new announcement from ARM that shows an amazing shift in thought and industry inertia.  ARM is partnering with Intel to introduce select products on Intel’s upcoming 10nm foundry process.  This news is both surprising and expected.  It is surprising in that it happened as quickly as it did.  It is expected as Intel is facing a very different world than it had planned for 10 years ago.  We could argue that it is much different than they planned for 5 years ago.

Intel is the undisputed leader in process technologies and foundry practices.  They are the gold standard of developing new, cutting edge process nodes and implementing them on a vast scale.  This has served them well through the years as they could provide product to their customers seemingly on demand.  It also allowed them a leg up in technology when their designs may not have fit what the industry wanted or needed (Pentium 4, etc.).  It also allowed them to potentially compete in the mobile market with designs that were not entirely suited for ultra-low power.  x86 is a modern processor technology with decades of development behind it, but that development focused mainly on performance at higher TDP ranges.

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This past year Intel signaled their intent to move out of the sub 5 watt market and cede it to ARM and their partners.  Intel’s ultra mobile offerings just did not make an impact in an area that they were expected to.  For all of Intel’s advances in process technology, the base ARM architecture is just better suited to these power envelopes.  Instead of throwing good money after bad (in the form of development time, wafer starts, rebates) Intel has stepped away from this market.

This leaves Intel with a problem.  What to do with extra production capacity?  Running a fab is a very expensive endeavor.  If these megafabs are not producing chips 24/7, then the company is losing money.  This past year Intel has seen their fair share of layoffs and slowing down production/conversion of fabs.  The money spent on developing new, cutting edge process technologies cannot stop for the company if they want to keep their dominant position in the CPU industry.  Some years back they opened up their process products to select 3rd party companies to help fill in the gaps of production.  Right now Intel has far more production line space than they need for the current market demands.  Yes, there were delays in their latest Skylake based processors, but those were solved and Intel is full steam ahead.  Unfortunately, they do not seem to be keeping their fabs utilized at the level needed or desired.  The only real option seems to be opening up some fab space to more potential customers in a market that they are no longer competing directly in.

The Intel Custom Foundry Group is working with ARM to provide access to their 10nm HPM process node.  Initial production of these latest generation designs will commence in Q1 2017 with full scale production in Q4 2017.  We do not have exact information as to what cores will be used, but we can imagine that they will be Cortex-A73 and A53 parts in big.LITTLE designs.  Mali graphics will probably be the first to be offered on this advanced node as well due to the Artisan/POP program.  Initial customers have not been disclosed and we likely will not hear about them until early 2017.

This is a big step for Intel.  It is also a logical progression for them when we look over the changing market conditions of the past few years.  They were unable to adequately compete in the handheld/mobile market with their x86 designs, but they still wanted to profit off of this ever expanding area.  The logical way to monetize this market is to make the chips for those that are successfully competing here.  This will cut into Intel’s margins, but it should increase their overall revenue base if they are successful here.  There is no reason to believe that they won’t be.

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The last question we have is if the 10nm HPM node will be identical to what Intel will use for their next generation “Cannonlake” products.  My best guess is that the foundry process will be slightly different and will not provide some of the “secret sauce” that Intel will keep for themselves.  It will probably be a mobile focused process node that stresses efficiency rather than transistor switching speed.  I could be very wrong here, but I don’t believe that Intel will open up their process to everyone that comes to them hat in hand (AMD).

The partnership between ARM and Intel is a very interesting one that will benefit customers around the globe if it is handled correctly from both sides.  Intel has a “not invented here” culture that has both benefited it and caused it much grief.  Perhaps some flexibility on the foundry side will reap benefits of its own when dealing with very different designs than Intel is used to.  This is a titanic move from where Intel probably thought it would be when it first started to pursue the ultra-mobile market, but it is a move that shows the giant can still positively react to industry trends.

IDF 2016: Intel To Demo Optane XPoint, Announces Optane Testbed for Enterprise Customers

Subject: Storage | August 16, 2016 - 02:00 PM |
Tagged: XPoint, Testbed, Optane, Intel, IDF 2016, idf

IDF 2016 is up and running, and Intel will no doubt be announcing and presenting on a few items of interest. Of note for this Storage Editor are multiple announcements pertaining to upcoming Intel Optane technology products.

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Optane is Intel’s branding of their joint XPoint venture with Micron. Intel launched this branding at last year's IDF, and while the base technology is as high as 1000x faster than NAND flash memory, full solutions wrapped around an NVMe capable controller have shown to sit at roughly a 10x improvement over NAND. That’s still nothing to sneeze at, and XPoint settles nicely into the performance gap seen between NAND and DRAM.

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Since modern M.2 NVMe SSDs are encroaching on the point of diminishing returns for consumer products, Intel’s initial Optane push will be into the enterprise sector. There are plenty of use cases for a persistent storage tier faster than NAND, but most enterprise software is not currently equipped to take full advantage of the gains seen from such a disruptive technology.

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XPoint die. 128Gbit of storage at a ~20nm process.

In an effort to accelerate the development and adoption of 3D XPoint optimized software, Intel will be offering enterprise customers access to an Optane Testbed. This will allow for performance testing and tuning of customers’ software and applications ahead of the shipment of Optane hardware.

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I did note something interesting in Micron's FMS 2016 presentation. QD=1 random performance appears to start at ~320,000 IOPS, while the Intel demo from a year ago (first photo in this post) showed a prototype running at only 76,600 IOPS. Using that QD=1 example, it appears that as controller technology improves to handle the large performance gains of raw XPoint, so does performance. Given a NAND-based SSD only turns in 10-20k IOPS at that same queue depth, we're seeing something more along the lines of 16-32x performance gains with the Micron prototype. Those with a realistic understanding of how queues work will realize that the type of gains seen at such low queue depths will have a significant impact in real-world performance of these products.

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The speed of 3D XPoint immediately shifts the bottleneck back to the controller, PCIe bus, and OS/software. True 1000x performance gains will not be realized until second generation XPoint DIMMs are directly linked to the CPU.

The raw die 1000x performance gains simply can't be fully realized when there is a storage stack in place (even an NVMe one). That's not to say XPoint will be slow, and based on what I've seen so far, I suspect XPoint haters will still end up burying their heads in the sand once we get a look at the performance results of production parts.

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Leaked roadmap including upcoming Optane products

Intel is expected to show a demo of their own more recent Optane prototype, and we suspect similar performance gains there as their controller tech has likely matured. We'll keep an eye out and fill you in once we've seen Intel's newer Optane goodness it in action!