Introduction, Dynamic Write Acceleration, and Packaging
Micron joined Intel in announcing their joint venture production of IMFT 3D NAND just a bit over a year ago. The industry was naturally excited since IMFT has historically enabled relatively efficient production, ultimately resulting in reduced SSD prices over time. I suspect this time things will be no different as IMFT's 3D Flash has been aiming high die capacities since its inception, and I suspect their second generation will *double* per-die capacities while keeping speeds reasonable thanks to a quad-plane design implemented from the start of this endeavor. Of course, I'm getting ahead of myself a bit as there are no consumer products sporting this flash just yet - well not until today at least:
Marketed under Micron's consumer brand Crucial, the MX300 is their first entrant into the consumer space, as well as the first consumer SSD sporting IMFT 3D NAND. Crucial is known for their budget-minded SSDs, and for the MX300 they chose to go with the best cost/GB they could manage with what they had to work with. That meant putting this new 3D NAND into TLC mode. Now there are many TLC haters out there, but remember this is 3D NAND. Samsung's 850 EVO can exceed 500 MB/sec writes to TLC at its 500GB capacity point, and this MX300 is a product that is launching with *only* a 750GB capacity, so its TLC speed should be at least reasonable.
(the return of) Dynamic Write Acceleration
Dynamic Write Acceleration in action during a sequential fill - that last slowest part was my primary concern for the mX300.
TLC is not the only story here because Crucial has included their Dynamic Write Acceleration (DWA) technology into the MX300. This is a tech where the SSD controller is able to dynamically switch flash programming modes of the flash pool, doing so at the block level. This appears to be a feature unique to IMFT flash, as every other 'hybrid' SSD we have tested had a static SLC cache area. DWA's ability to switch flash modes on-the-fly has always fascinated me on paper, but I just haven't been impressed by Micron's previous attempts to implement it. The M600 was a bit all over the place on its write consistency, and that SSD was flipping blocks between SLC and MLC. With the MX300 flipping between SLC and *TLC*, there was a possibility of far more noticeable slow downs in the cases where large writes were taking place and the controller was caught trying to scavenge space in the background.
New Latency Percentile vs. legacy IO Percentile, shown here highlighting a performance inconsistency seen in the Toshiba OCZ RD400. Note which line more closely represents the Latency Distribution (gray) also on this plot.
Subject: Storage | June 13, 2016 - 03:46 AM | Allyn Malventano
Tagged: XPoint, tlc, Stony Beach, ssd, pcie, Optane, NVMe, mlc, Mansion Beach, M.2, kaby lake, Intel, imft, Brighton Beach, 3DNAND, 3d nand
For those unaware, XPoint (spoken 'cross-point') is a new type of storage technology that is persistent like NAND Flash but with speeds closer to that of RAM. Intel's brand name for devices implementing XPoint are called Optane.
Starting at the bottom of the slide, we see a new 'System Acceleration' segment with a 'Stony Beach PCIe/NVMe m.2 System Accelerator'. This is likely a new take on Larson Creek, which was a 20GB SLC SSD launched in 2011. This small yet very fast SLC flash was tied into the storage subsystem via Intel's Rapid Storage Technology and acted as a caching tier for HDDs, which comprised most of the storage market at that time. Since Optane excels at random access, even a PCIe 3.0 x2 part could outmaneuver the fastest available NAND, meaning these new System Accelerators could act as a caching tier for Flash-based SSDs or even HDDs. These accelerators can also be good for boosting the performance of mobile products, potentially enabling the use of cheaper / lower performing Flash / HDD for bulk storage.
Skipping past the mainstream parts for now, enthusiasts can expect to see Brighton Beach and Mansion Beach, which are Optane SSDs linked via PCIe 3x2 or x4, respectively. Not just accelerators, these products should have considerably more storage capacity, which may bring costs fairly high unless either XPoint production is very efficient or if there is also NAND Flash present on those parts for bulk storage (think XPoint cache for NAND Flash all in one product).
We're not sure if or how the recent delays to Kaby Lake will impact the other blocks on the above slide, but we do know that many of the other blocks present are on-track. The SSD 540s and 5400s were in fact announced in Q2, and are Intel's first shipping products using IMFT 3D NAND. Parts not yet seen announced are the Pro 6000p and 600p, which are long overdue m.2 SSDs that may compete against Samsung's 950 Pro. Do note that those are marked as TLC products (purple), though I suspect they may actually be a hybrid TLC+SLC cache solution.
Going further out on the timeline we naturally see refreshes to all of the Optane parts, but we also see the first mention of second-generation IMFT 3DNAND. As I hinted at in an article back in February, second-gen 3D NAND will very likely *double* the per-die capacity to 512Gbit (64GB) for MLC and 768Gbit (96GB) for TLC. While die counts will be cut in half for a given total SSD capacity, speed reductions will be partially mitigated by this flash having at least four planes per die (most previous flash was double-plane). A plane is an effective partitioning of flash within the die, with each section having its own buffer. Each plane can perform erase/program/read operations independently, and for operations where the Flash is more limiting than the interface (writes), doubling the number of planes also doubles the throughput. In short, doubling planes roughly negates the speed drop caused by halving the die count on an SSD (until you reach the point where controller-to-NAND channels become the bottleneck, of course).
IMFT XPoint Die shot I caught at the Intel / Micron launch event.
Well, that's all I have for now. I'm excited to see that XPoint is making its way into consumer products (and Storage Accelerators) within the next year's time. I certainly look forward to testing these products, and I hope to show them running faster than they did back at that IDF demo...
Subject: Storage | February 14, 2016 - 02:51 PM | Allyn Malventano
Tagged: vnand, ssd, Samsung, nand, micron, Intel, imft, 768Gb, 512GB, 3d nand, 384Gb, 32 Layer, 256GB
You may have seen a wave of Micron 3D NAND news posts these past few days, and while many are repeating the 11-month old news with talks of 10TB/3.5TB on a 2.5"/M.2 form factor SSDs, I'm here to dive into the bigger implications of what the upcoming (and future) generation of Intel / Micron flash will mean for SSD performance and pricing.
Remember that with the way these capacity increases are going, the only way to get a high performance and high capacity SSD on-the-cheap in the future will be to actually get those higher capacity models. With such a large per-die capacity, smaller SSDs (like 128GB / 256GB) will suffer significantly slower write speeds. Taking this upcoming Micron flash as an example, a 128GB SSD will contain only four flash memory dies, and as I wrote about back in 2014, such an SSD would likely see HDD-level sequential write speeds of 160MB/sec. Other SSD manufacturers already recognize this issue and are taking steps to correct it. At Storage Visions 2016, Samsung briefed me on the upcoming SSD 750 Series that will use planar 16nm NAND to produce 120GB and 250GB capacities. The smaller die capacities of these models will enable respectable write performance and will also enable them to discontinue their 120GB 850 EVO as they transition that line to higher capacity 48-layer VNAND. Getting back to this Micron announcement, we have some new info that bears analysis, and that pertains to the now announced page and block size:
256Gb MLC: 16KB Page / 16MB Block / 1024 Pages per Block
384Gb TLC: 16KB Page / 24MB Block / 1536 Pages per Block
To understand what these numbers mean, using the MLC line above, imagine a 16MB CD-RW (Block) that can write 1024 individual 16KB 'sessions' (Page). Each 16KB can be added individually over time, and just like how files on a CD-RW could be modified by writing a new copy in the remaining space, flash can do so by writing a new Page and ignoring the out of date copy. Where the rub comes in is when that CD-RW (Block) is completely full. The process at this point is very similar actually, in that the Block must be completely emptied before the erase command (which wipes the entire Block) is issued. The data has to go somewhere, which typically means writing to empty blocks elsewhere on the SSD (and in worst case scenarios, those too may need clearing before that is possible), and this moving and erasing takes time for the die to accomplish. Just like how wiping a CD-RW took a much longer than writing a single file to it, erasing a Block takes typically 3-4x as much time as it does to program a page.
With that explained, of significance here are the growing page and block sizes in this higher capacity flash. Modern OS file systems have a minimum bulk access size of 4KB, and Windows versions since Vista align their partitions by rounding up to the next 2MB increment from the start of the disk. These changes are what enabled HDDs to transition to Advanced Format, which made data storage more efficient by bringing the increment up from the 512 Byte sector up to 4KB. While most storage devices still use 512B addressing, it is assumed that 4KB should be the minimum random access seen most of the time. Wrapping this all together, the Page size (minimum read or write) is 16KB for this new flash, and that is 4x the accepted 4KB minimum OS transfer size. This means that power users heavy on their page file, or running VMs, or any other random-write-heavy operations being performed over time will have a more amplified effect of wear of this flash. That additional shuffling of data that must take place for each 4KB write translates to lower host random write speeds when compared to lower capacity flash that has smaller Page sizes closer to that 4KB figure.
A rendition of 3D IMFT Floating Gate flash, with inset pulling back some of the tunnel oxide layer to show the location of the floating gate. Pic courtesy Schiltron.
Fortunately for Micron, their choice to carry Floating Gate technology into their 3D flash has netted them some impressive endurance benefits over competing Charge Trap Flash. One such benefit is a claimed 30,000 P/E (Program / Erase) cycle endurance rating. Planar NAND had dropped to the 3,000 range at its lowest shrinks, mainly because there was such a small channel which could only store so few electrons, amplifying the (negative) effects of electron leakage. Even back in the 50nm days, MLC ran at ~10,000 cycle endurance, so 30,000 is no small feat here. The key is that by using that same Floating Gate tech so good at controlling leakage for planar NAND on a new 3D channel that can store way more electrons enables excellent endurance that may actually exceed Samsung's Charge Trap Flash equipped 3D VNAND. This should effectively negate the endurance hit on the larger Page sizes discussed above, but the potential small random write performance hit still stands, with a possible remedy being to crank up the Over-Provisioning of SSDs (AKA throwing flash at the problem). Higher OP means less active pages per block and a reduction in the data shuffling forced by smaller writes.
A 25nm flash memory die. Note the support logic (CMOS) along the upper left edge.
One final thing helping out Micron here is that their Floating Gate design also enables a shift of 75% of the CMOS circuitry to a layer *underneath* the flash storage array. This logic is typically part of what you see 'off to the side' of a flash memory die. Layering CMOS logic in such a way is likely thanks to Intel's partnership and CPU development knowledge. Moving this support circuitry to the bottom layer of the die makes for less area per die dedicated to non-storage, more dies per wafer, and ultimately lower cost per chip/GB.
Samsung's Charge Trap Flash, shown in both planar and 3D VNAND forms.
One final thing before we go. If we know anything about how the Intel / Micron duo function, it is that once they get that freight train rolling, it leads to relatively rapid advances. In this case, the changeover to 3D has taken them a while to perfect, but once production gains steam, we can expect to see some *big* advances. Since Samsung launched their 3D VNAND their gains have been mostly iterative in nature (24, 32, and most recently 48). I'm not yet at liberty to say how the second generation of IMFT 3D NAND will achieve it, but I can say that it appears the next iteration after this 32-layer 256Gb (MLC) /384Gb (TLC) per die will *double* to 512Gb/768Gb (you are free to do the math on what that means for layer count). Remember back in the day where Intel launched new SSDs at a fraction of the cost/GB of the previous generation? That might just be happening again within the next year or two.
Subject: Storage, Shows and Expos | January 6, 2016 - 06:00 AM | Allyn Malventano
Tagged: tlc, SM2260, SM2258, SM2256, SM2246EN, slc, SK Hynix, silicon motion, mlc, micron, Intel, imft, CES 2016, CES, 3d nand
Silicon Motion has updated their popular SM2246EN controller to support MLC 3D NAND from IMFT and SK Hynix:
The SM2246EN acts as a gateway for third parties to make their own SSDs. Adding support for 3D NAND is good news, as it means we will be able to see third party SSDs launch with 3D flash sourced from Intel, Micron, or SK Hynix. Another cool tidbit is the fact that those demo units in the above photo were equipped and operating with actual 3D NAND from Intel, Micron, and SK Hynix. Yes, this is the first time seeing packaged MLC 3D NAND from a company other than Samsung. Here are some close-ups for those who want to read part numbers:
Another question on non-Samsung 3D NAND is how does its performance stack up against planar (2D) NAND? Silicon Motion had a bit of an answer to that question for us:
Keep in mind those are results from pre-production firmware, but I was happy to see that my prediction of IMFT 3D NAND speeds being effectively equal to their previous 2D flash was correct.
To knock out some other info overheard at our briefing, Silicon Motion will also be making an SM2258, which will be a TLC 3D NAND variant of the SM2256. In addition, we saw the unreleased SM2260:
...which is Silicon Motion's PCIe 3.0 x4 SSD controller. This one is expected to surface towards the middle of 2016, and it is currently in the OEM testing stage.
Lots more storage goodies coming later today, so stay tuned! Full press blast for the updates SM2246EN after the break.
Follow all of our coverage of the show at http://pcper.com/ces!
Subject: Storage | March 26, 2015 - 02:12 PM | Sebastian Peak
Tagged: storage, ssd, planar, nand, micron, M.2, Intel, imft, floating-gate, 3d nand
Intel and Micron are jointly announcing new 3D NAND technology that will radically increase solid-storage capacity going forward. The companies have indicated that moving to this technology will allow for the type of rapid increases in capacity that are consistent with Moore’s Law.
The way Intel and Micron are approaching 3D NAND is very different from existing 3D technologies from Samsung and now Toshiba. The implementation of floating-gate technology and “unique design choices” has produced startling densities of 256 Gb MLC, and a whopping 384 Gb with TLC. The choice to base this new 3D NAND on floating-gate technology allows development with a well-known entity, and benefits from the knowledge base that Intel and Micron have working with this technology on planar NAND over their long partnership.
What does this mean for consumers? This new 3D NAND enables greater than 10TB capacity on a standard 2.5” SSD, and 3.5TB on M.2 form-factor drives. These capacities are possible with the industry’s highest density 3D NAND, as the >3.5TB M.2 capacity can be achieved with just 5 packages of 16 stacked dies with 384 Gb TLC.
A 3D NAND cross section from Allyn's Samsung 850 Pro review
While such high density might suggest reliance on ever-shrinking process technology (and the inherent loss of durability thus associated) Intel is likely using a larger process for this NAND. Though they would not comment on this, Intel could be using something roughly equivalent to 50nm flash with this new 3D NAND. In the past die shrinks have been used to increase capacity per die (and yields) such as IMFT's move to 20nm back in 2011, but with the ability to achieve greater capacity vertically using 3D cell technology a smaller process is not necessary to achieve greater density. Additionally, working with a larger process would allow for better endurance as, for example, 50nm MLC was on the order of 10,000 program/erase cycles. Samsung similarly moved to a larger process with with their initial 3D NAND, moving from their existing 20nm technology back to 30nm with 3D production.
This announcement is also interesting considering Toshiba has just entered this space as well having announced 48-layer 128 Gb density 3D NAND, and like Samsung, they are moving away from floating-gate and using their own charge-trap implementation they are calling BiCS (Bit Cost Scaling). However with this Intel/Micron announcement the emphasis is on the ability to offer a 3x increase in capacity using the venerable floating-gate technology from planar NAND, which gives Intel / Micron an attractive position in the market - depending on price/performance of course. And while these very large capacity drives seem destined to be expensive at first, the cost structure is likely to be similar to current NAND. All of this remains to be seen, but this is indeed promising news for the future of flash storage as it will now scale up to (and beyond) spinning media capacity - unless 3D tech is implemented in hard drive production, that is.
So when will Intel and Micron’s new technology enter the consumer market? It could be later this year as Intel and Micron have already begun sampling the new NAND to manufacturers. Manufacturing has started in Singapore, plus ground has also been broken at the IMFT fab in Utah to support production here in the United States.
Subject: General Tech, Memory, Systems | February 10, 2013 - 03:44 AM | Scott Michaud
Tagged: NVDIMM, micron, IMFT NAND, imft
So a RAM chip, a NAND module, and an “ultracapacitor” walk into stick...
This week Micron released a press blast for technology called, “NVDIMM”. The goal is to create memory modules which perform as quickly as DRAM but can persist without power. At this point you could probably guess the acronym: Nonvolatile Dual In-line Memory Module. It has been around for a few years now, but it is in the news now so let's chat about it.
I often like to play the game, “Was this named by an engineer or a marketer?” You can typically tell who was responsible for naming something by gauging how literally it breaks down into a simple meaning versus not having any apparent meaning at all. A good example of an engineer name is UHF, which breaks down into ultra-high frequency because it's higher than VHF, very-high frequency. A good example of a marketing name would be something like “Centrino”, which sounds like the biggest little penny-slot machine in the world. I would quite comfortable guessing that NVDIMM was named by an engineer.
This is AgigA Tech's module, who provides the capacitors for Micron and their NVDIMMs.
The actual makeup of NVDIMMs is quite sensible: DIMMs are fast but die when the power goes out. You could prevent the power from going out but it takes quite a lot of battery life to keep a computer online for extended periods of time. NAND Flash is quite slow, relative to DIMMs, in normal operation but can persist without power for very long periods of time. Also, modern-day capacitors are efficient and durable enough to keep DIMMs powered for long enough to be copied to flash memory.
As such, if the power goes out: memory is dumped to flash on the same chip. When power is restored, DIMMs get reloaded and continue on their merry way.
According to the Micron press release, the first NVDIMM was demonstrated last November at SC12. That module contained twice as much NAND as it did DIMM memory: 8GB of Flash for 4GB of RAM. Micron did not specify why they required having that much extra Flash memory although my gut instinct is to compensate for write wearing problems. A two-fold increase to offset NAND that had just one too many write operations seems like quite a lot compared to consumer drives. That said, SSDs do not have to weather half of their whole capacity being written to each time the computer shuts down.
Who knows, double-provisioning might even be too little in practice.
Subject: Storage | February 28, 2012 - 05:40 PM | Allyn Malventano
Tagged: micron, Intel, imft, flash, fab
Earlier today we caught some news of Intel and Micron extending their joint agreement to develop and create flash memory under the IMFT name. Along with this extension came some rearrangements to the current plan. Intel will be selling off their stake in two of the smaller fabs, located in Singapore and Manassas, VA. The sale is for $600 million, half of which will stay with Micron as a credit that Intel can use to later purchase NAND flash produced from those factories.
The 'tip of the spear' IMFT fab located in Lehi, Utah, will remain jointly owned and operated. This makes good business sense as the Lehi fab is the first to shift to smaller process nodes. IMFT announced 25nm flash memory production at this very fab in early 2010.
PC Perspective toured IMFT Utah during the 25nm launch announcement.
Some may see this as Intel taking a step away from flash memory, but I see it as quite the contrary. Micron has always tended towards being a bulk producer of memory products, while Intel are the promary innovators in the arena. This move allows Intel to focus on the bleeding edge plant while Micron handles the particulars of cranking out those technologies developed at the Lehi Plant. It is likely that the highest grade flash comes from the Lehi plant, and Intel's half of the output is more than enough to supply their SSD production lines.
Subject: Storage, Shows and Expos | January 16, 2012 - 05:33 PM | Allyn Malventano
Tagged: ssd, micron, Intel, imft, flash, cherryville, CES, 20nm
CES is sort of like a Where's Waldo book. There are thousands of places to look, with new technology spread around all over the place. Some of that unreleased tech shows up right in front of you and you don't even realize what you were looking at until later on. It's how we caught a look at prototype Light Peak (now Thunderbolt) two years ago, and this year we saw some more goodies not previously seen in the wild. I tend to be a bit of a shutterbug, and I take seemingly random pics of things as the PCPer gang runs around the various vendor booths and hotel suites. While going through the pics from my phone, I ran across this shot of what I thought was an Intel 320 Series SSD:
Definitely not a 320, that's an Intel 520 Series (Cherryville) SSD. While Intel had their 520 Series locked up tight at their Storage Visions booth, this one was powering another motherboard makers product elsewhere in Vegas. Unfortunately this system was only to demo the motherboard itself, without a connected display, so it would not have been possible to run our own benches.
At storage visions, we also saw this display at the Micron booth. It's interesting to see how 16GB of flash memory has shrunk over the past few years. We've certainly come a long way from the good old X25-M:
Some of you may know that I'm a sucker for a good die shot, so I snuck back out to Micron's suite later on to get my own macro shot of the 20nm IMFT flash die:
Micron is, like many other vendors, working on their own SSD solution specifically for SSD caching applications. It's currently unreleased, so more to follow on this.
PC Perspective's CES 2012 coverage is sponsored by MSI Computer.
Follow all of our coverage of the show at http://pcper.com/ces!