Manufacturer: Intel

Core and Interconnect

The Skylake architecture is Intel’s first to get a full release on the desktop in more than two years. While that might not seem like a long time in the grand scheme of technology, for our readers and viewers that is a noticeable change and shift from recent history that Intel has created with the tick-tock model of releases. Yes, Broadwell was released last year and was solid product, but Intel focused almost exclusively on the mobile platforms (notebooks and tablets) with it. Skylake will be much more ubiquitous and much more quickly than even Haswell.

Skylake represents Intel’s most scalable architecture to date. I don’t mean only frequency scaling, though that is an important part of this design, but rather in terms of market segment scaling. Thanks to brilliant engineering and design from Intel’s Israeli group Intel will be launching Skylake designs ranging from 4.5 watt TDP Core M solutions all the way up to the 91 watt desktop processors that we have already reviewed in the Core i7-6700K. That’s a range that we really haven’t seen before and in the past Intel has depended on the Atom architecture to make up ground on the lowest power platforms. While I don’t know for sure if Atom is finally trending towards the dodo once Skylake’s reign is fully implemented, it does make me wonder how much life is left there.


Scalability also refers to the package size – something that ensures that the designs the engineers created can actually be built and run in the platform segments they are targeting. Starting with the desktop designs for LGA platforms (DIY market) that fits on a 1400 mm2 design on the 91 watt TDP implementation Intel is scaling all the way down to 330 mm2 in a BGA1515 package for the 4.5 watt TDP designs. Only with a total product size like that can you hope to get Skylake in a form factor like the Compute Stick – which is exactly what Intel is doing. And note that the smaller packages require the inclusion of the platform IO chip as well, something that H- and S-series CPUs can depend on the motherboard to integrate.

Finally, scalability will also include performance scaling. Clearly the 4.5 watt part will not offer the user the same performance with the same goals as the 91 watt Core i7-6700K. The screen resolution, attached accessories and target applications allow Intel to be selective about how much power they require for each series of Skylake CPUs.

Core Microarchitecture

The fundamental design theory in Skylake is very similar to what exists today in Broadwell and Haswell with a handful of significant and hundreds of minor change that make Skylake a large step ahead of previous designs.


This slide from Julius Mandelblat, Intel Senior Principle Engineer, shows a higher level overview of the entirety of the consumer integration of Skylake. You can see that Intel’s goals included a bigger and wider core design, higher frequency, improved right architecture and fabric design and more options for eDRAM integration. Readers of PC Perspective will already know that Skylake supports both DDR3L and DDR4 memory technologies but the inclusion of the camera ISP is new information for us.

Continue reading our overview of the Intel Skylake microarchitecture!!

Podcast #318 - GTX 980 and R9 390X Rumors, Storage News from IDF, ADATA SP610 SSDs and more!

Subject: General Tech | September 18, 2014 - 01:59 PM |
Tagged: windows 9, video, TSV, supernova, raptr, r9 390x, podcast, p3700, nvidia, Intel, idf, GTX 980, evga, ECS, ddr4, amd

PC Perspective Podcast #318 - 09/18/2014

Join us this week as we discuss GTX 980 and R9 390X Rumors, Storage News from IDF, ADATA SP610 SSDs and more!

You can subscribe to us through iTunes and you can still access it directly through the RSS page HERE.

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Hosts: Ryan Shrout, Jeremy Hellstrom, Josh Walrath, and Allyn Malventano

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IDF 2014 Storage Roundup - RAM and NVMe and IOPS! Oh my!

Subject: Storage, Shows and Expos | September 16, 2014 - 12:49 PM |
Tagged: ram, NVMe, IOPS, idf 2014, idf, ddr4, DDR

The Intel Developer Forum was last week, and there were many things to be seen for sure. Mixed in with all of the wearable and miniature technology news, there was a sprinkling of storage goodness. Kicking off the show, we saw new cold storage announcements from both HGST and Western Digital, but that was about it for HDD news, as the growing trend these days is with solid state storage technologies. I'll start with RAM:

First up was ADATA, who were showing off 64GB DDR3 (!) DIMMs:


Next up were various manufacturers pushing DDR4 technology quite far. First was SK Hynix's TSV 128GB DIMMs (covered in much greater depth last week):


Next up is Kingston, who were showing a server chassis equipped with 256GB of DDR4:


If you look closer at the stats, you'll note there is more RAM in this system than flash:


Next up is IDT, who were showing off their LRDIMM technology:


This technology adds special data buffers to the DIMM modules, enabling significantly higher amounts of installed RAM into a single system, with a 1-2 step de-rating of clock speeds as you take capacities to the far extremes. The above server has 768GB of DDR4 installed and running!:


Moving onto flash memory type stuff, Scott covered Intel's new 40 Gbit Ethernet technology last week. At IDF, Intel had a demo showing off some of the potential of these new faster links:


This demo used a custom network stack that allowed a P3700 in a local system to be matched in IOPS by an identical P3700 *being accessed over the network*. Both local and networked storage turned in the same 450k IOPS, with the remote link adding only 8ms of latency. Here's a close-up of one of the SFF-8639 (2.5" PCIe 3.0 x4) SSDs and the 40 Gbit network card above it (low speed fans were installed in these demo systems to keep some air flowing across the cards):


Stepping up the IOPS a bit further, Microsoft was showing off the capabilities of their 'Inbox AHCI driver', shown here driving a pair of P3700's at a total of 1.5 million IOPS:


...for those who want to get their hands on this 'Inbox driver', guess what? You already have it! "Inbox" is Microsoft's way of saying the driver is 'in the box', meaning it comes with Windows 8. Bear in bind you may get better performance with manufacturer specific drivers, but it's still a decent showing for a default driver.

Now for even more IOPS:


Yes, you are reading that correctly. That screen is showing a system running over 11 million IOPS. Think it's RAM? Wrong. This is flash memory pulling those numbers. Remember the 2.5" P3700 from a few pics back? How about 24 of them:


The above photo shows three 2U systems (bottom), which are all connected to a single 2U flash memory chassis (top). The top chassis supports three submodules, each with eight SFF-8639 SSDs. The system, assembled by Newisys, demonstrates just how much high speed flash you can fit within an 8U space. The main reason for connecting three systems to one flash chassis is because it takes those three systems to process the full IOPS capability of 24 low latency NVMe SSDs (that's 96 total lanes of PCIe 3.0!)!

So there you have it, IDF storage tech in a nutshell. More to come as we follow these emerging technologies to their maturity.

Intel Loves Exponential Trends: Shrinking Mini-PCs

Subject: General Tech, Cases and Cooling, Systems, Shows and Expos | September 12, 2014 - 02:20 PM |
Tagged: idf, idf 2014, nuc, Intel, SFF, small form factor

A few years ago, Intel introduced the NUC line of small form factor PCs. At this year's IDF, they have announced plans to make even smaller, and cheaper, specifications that are intended for OEMs to install Windows, Linux, Android, and Chrome OS on. This initiative is not yet named, but will consist of mostly soldered components, leaving basically just the wireless adapters user-replaceable, rather than the more user-serviceable NUC.


Image Credit: Liliputing

Being the owner of Moore's Law, they just couldn't help but fit it to some type of exponential curve. While it is with respect to generation, not time, Intel expects the new, currently unnamed form factor to halve both the volume (size) and bill of material (BOM) cost of the NUC. They then said that another generation after ("Future SFF") will halve the BOM cost again, to a quarter of the NUC.

What do our readers think? Would you be willing to give up socketed components for smaller and cheaper devices in this category or does this just become indistinguishable from mobile devices (which we already know can be cheap and packed into small spaces)?

Source: Liliputing

Podcast #317 - ASUS X99 Deluxe Review, Core M Performance, 18 Core Xeons and much more news from IDF!

Subject: General Tech | September 11, 2014 - 02:30 PM |
Tagged: podcast, video, asus, X99, X99 Deluxe, Intel, core m, xeon e5-2600 v3, idf, idf 2014, fortville, 40GigE, dell, 5k, nvidia, GM204, maxwell

PC Perspective Podcast #317 - 09/11/2014

Join us this week as we discuss our ASUS X99 Deluxe Review, Core M Performance, 18 Core Xeons and much more news from IDF!

You can subscribe to us through iTunes and you can still access it directly through the RSS page HERE.

The URL for the podcast is: - Share with your friends!

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  • RSS - Subscribe through your regular RSS reader
  • MP3 - Direct download link to the MP3 file

Hosts: Josh Walrath, Allyn Malventano, and Morry Tietelman

Program length: 1:33:48

  1. Week in Review:
  2. IDF News:
  3. News items of interest:
  4. Hardware/Software Picks of the Week:
    1. Allyn: Read our IDF news!
  5. Closing/outro

Subscribe to the PC Perspective YouTube Channel for more videos, reviews and podcasts!!


IDF 2014: Through Silicon Via - Connecting memory dies without wires

Subject: Storage, Shows and Expos | September 10, 2014 - 03:34 PM |
Tagged: TSV, Through Silicon Via, memory, idf 2014, idf

If you're a general computer user, you might have never heard the term "Through Silicon Via". If you geek out on photos of chip dies and wafers, and how chips are assembled and packaged, you might have heard about it. Regardless of your current knowledge of TSV, it's about to be a thing that impacts all of you in the near future.

Let's go into a bit of background first. We're going to talk about how chips are packaged. Micron has an excellent video on the process here:

The part we are going to focus on appears at 1:31 in the above video:

die wiring.png

This is how chip dies are currently connected to the outside world. The dies are stacked (four high in the above pic) and a machine has to individually wire them to a substrate, which in turn communicates with the rest of the system. As you might imagine, things get more complex with this process as you stack more and more dies on top of each other:

chip stacking.png

16 layer die stack, pic courtesy NovaChips we have these microchips with extremely small features, but to connect them we are limited to a relatively bulky process (called package-on-package). Stacking these flat planes of storage is a tricky thing to do, and one would naturally want to limit how many of those wires you need to connect. The catch is that those wires also equate to available throughput from the device (i.e. one wire per bit of a data bus). So, just how can we improve this method and increase data bus widths, throughput, etc?

Before I answer that, let me lead up to it by showing how flash memory has just taken a leap in performance. Samsung has recently made the jump to VNAND:

vnand crop--.png

By stacking flash memory cells vertically within a die, Samsung was able to make many advances in flash memory, simply because they had more room within each die. Because of the complexity of the process, they also had to revert back to an older (larger) feature size. That compromise meant that the capacity of each die is similar to current 2D NAND tech, but the bonus is speed, longevity, and power reduction advantages by using this new process.

I showed you the VNAND example because it bears a striking resemblance to what is now happening in the area of die stacking and packaging. Imagine if you could stack dies by punching holes straight through them and making the connections directly through the bottom of each die. As it turns out, that's actually a thing:

tsv cross section.png

Read on for more info about TSV!

Manufacturer: Intel

Core M 5Y70 Early Testing

During a press session today with Intel, I was able to get some early performance results on Broadwell-Y in the form of the upcoming Core M 5Y70 processor.


Testing was done on a reference design platform code named Llama Mountain and at the heart of the system is the Broadwell-Y designed dual-core CPU, the Core M 5Y70, which is due out later this year. Power consumption of this system is low enough that Intel has built it with a fanless design. As we posted last week, this processor has a base frequency of just 1.10 GHz but it can boost as high as 2.6 GHz for extra performance when it's needed.

Before we dive into the actual result, you should keep in mind a couple of things. First, we didn't have to analyze the systems to check driver revisions, etc., so we are going on Intel's word that these are setup as you would expect to see them in the real world. Next, because of the disjointed nature of test were were able to run, the comparisons in our graphs aren't as great as I would like. Still, the results for the Core M 5Y70 are here should you want to compare them to any other scores you like.

First, let's take a look at old faithful: CineBench 11.5.


UPDATE: A previous version of this graph showed the TDP for the Intel Core M 5Y70 as 15 watts, not the 4.5 watt listed here now. The reasons are complicated. Even though the Intel Ark website lists the TDP of the Core M 5Y70, Intel has publicly stated the processor will make very short "spikes" at 15 watts when in its highest Turbo Boost modes. It comes to a discussion of semantics really. The cooling capability of the tablet is only targeted to 4.5-6.0 watts and those very short 15 watt spikes can be dissipated without the need for extra heatsink surface...because they are so short. SDP anyone? END UPDATE

With a score of 2.77, the Core M 5Y70 processor puts up an impressive fight against CPUs with much higher TDP settings. For example, Intel's own Pentium G3258 gets a score of 2.71 in CB11, and did so with a considerably higher thermal envelope. The Core i3-4330 scores 38% higher than the Core M 5Y70 but it requires a TDP 3.6-times larger to do so. Both of AMD's APUs in the 45 watt envelope fail to keep up with Core M.

Continue reading our preview of Intel Core M 5Y70 Performance!!

IDF 2014: Skylake Silicon Up and Running for 2H 2015 Release

Subject: Shows and Expos | September 9, 2014 - 05:27 PM |
Tagged: Skylake, Intel, idf 2014, idf, 14nm

2015 is shaping up to be an interesting year for Intel's consumer processor product lines. We are still expected to see Broadwell make some kind of debut in a socketed form in addition to the mobile releases trickling out beginning this holiday, but it looks like we will also get our first taste of Skylake late next year.


Skylake is Intel's next microarchitecture and will be built on the same 14nm process technology currently shipping with Broadwell-Y. Intel stated that it expects to see dramatic improvements in all areas of measurement including performance, power consumption and silicon efficiency.

On stage the company demoed Skylake running the 3DMark Fire Strike benchmark though without providing any kind of performance result (obviously). That graphics demo was running on an engineering development board and platform and though it looked incredibly good from where we were sitting, we can't make any guess as to the performance quite yet.


Intel then surprised us by bringing a notebook out from behind the monitor showing Skylake up and running in a mobile form factor decoding and playing back 4K video. Once again, the demo was smooth and impressive though you expect no more from an overly rehearsed keynote.


Intel concluded that it was "excited about the health of Skylake" and that they should be in mass production in the first quarter of 2015 with samples going out to customers. Looking even further down the rabbit hole the company believes they have a "great line of sight to 10nm and beyond." 

Even though details were sparse, it is good news for Intel that they would be willing to show Skylake so early and yet I can't help but worry about a potentially shorter-than-expected life span for Broadwell in the desktop space. Mobile users will find the increased emphasis on power efficiency a big win for thin and light notebooks but enthusiast are still on the look out for a new product to really drive performance up in the mainstream.

IDF 2014: Western Digital announces new Ae HDD series for archival / cold storage

Subject: Storage, Shows and Expos | September 9, 2014 - 04:51 PM |
Tagged: WDC< Western Digital, WD, idf 2014, idf, hdd, Cold, Archival, Ae

We talked about helium filled, shingled HDD's from HGST earlier today. Helium may give you reduced power demands, but at the added expensive of hermetically sealed enclosures over conventional HDD's. Shingling may give added capacity, but at the expense of being forced into specific writing methods. Now we know Western Digital's angle into archival / cold storage:

WD_AE_PRN.jpg instead of going with higher cost newer technologies, WD is taking their consumer products and making them more robust. They are also getting rid of the conventional thinking of capacity increments and are moving to 100GB increments. The idea is that once a large company or distributor has qualified a specific HDD model on their hardware, that model will stick around for a while, but be continued at an increased capacity as platter density yields increase over time. WD has also told me that capacities may even be mixed an matched within a 20-box of drives, so long as the average capacity matches the box label. This works in the field of archival / cold storage for a few reasons:

  • Archival storage systems generally do not use conventional RAID (where an entire array of matching capacity disks are spinning simultaneously). Drives are spun up and written to individually, or spun up individually to service the occasional read request. This saves power overall, and it also means the individual drives can vary in capacity with no ill effects.
  • Allowing for variable capacity binning helps WD ship more usable platters/drives overall (i.e. not rejecting drives that can't meet 6TB). This should drive overall costs down.
  • Increasing capacity by only a few hundred GB per drive turns into *huge* differences in cost when you scale that difference up to the number of drives you would need to handle a very large total capacity (i.e. Exabytes).

So the idea here is that WD is choosing to stick with what they do best, which they can potentially do for even cheaper than their consumer products. That said, this is really meant for enterprise use and not as a way for a home power user to save a few bucks on a half-dozen drives for their home NAS. You really need an infrastructure in place that can handle variable capacity drives seamlessly. While these drives do not employ SMR to get greater capacity, that may work out as a bonus, as writes can be performed in a way that all systems are currently compatible with (even though I suspect they will be tuned more for sequential write workloads).

Here's an illustration of this difference:

capacity 1.png

The 'old' method meant that drives on the left half of the above bell curve would have to be sold as 5TB units.

capacity 2.png

With the 'new' method, drives can be sold based on a spec closer to their actual capacity yield. For a given model, shipping capacities would increase as time goes on (top to bottom of the above graphic).

To further clarify what is meant by the term 'cold storage' - the data itself is cold, as in rarely if ever accessed:


Examples of this would be Facebook posts / images from months or years ago. That data may be rarely touched, but it needs to be accessible enough to be browsed to via the internet. The few second archival HDD spinup can handle this sort of thing, while a tape system would take far too long and would likely timeout that data request.

WD's Ae press blast after the break.

IDF 2014: HGST announces 3.2TB NVMe SSDs, shingled 10TB HDDs

Subject: Storage, Shows and Expos | September 9, 2014 - 02:00 PM |
Tagged: ssd, SMR, pcie, NVMe, idf 2014, idf, hgst, hdd, 10TB

It's the first day of IDF, so it's only natural that we see a bunch of non-IDF news start pouring out :). I'll kick them off with a few announcements from HGST. First item up is their new SN100 line of PCIe SSDs:


These are NVMe capable PCIe SSDs, available from 800GB to 3.2TB capacities and in (PCI-based - not SATA) 2.5" as well as half-height PCIe cards.

Next up is an expansion of their HelioSeal (Helium filled) drive line:


Through the use of Shingled Magnetic Recording (SMR), HGST can make an even bigger improvement in storage densities. This does not come completely free, as due to the way SMR writes to the disk, it is primarily meant to be a sequential write / random access read storage device. Picture roofing shingles, but for hard drives. The tracks are slightly overlapped as they are written to disk. This increases density greatly, but writting to the middle of a shingled section is not possible without potentially overwriting two shingled tracks simultaneously. Think of it as CD-RW writing, but for hard disks. This tech is primarily geared towards 'cold storage', or data that is not actively being written. Think archival data. The ability to still read that data randomly and on demand makes these drives more appealing than retrieving that same data from tape-based archival methods.

Further details on the above releases is scarce at present, but we will keep you posted on further details as they develop.

Full press blast for the SN100 after the break.

Source: HGST