AMD is making SeaMicro walk the plank

Subject: General Tech | April 20, 2015 - 01:17 PM |
Tagged: amd, seamicro, HPC

Just over three years ago AMD purchased SeaMicro for $334 million to give them a way to compete in HPC applications against Intel who had recently bought up QLogic and the InfiniBand interconnect technology.  The purchase of SeaMicro included their Freedom Fabric technology which was at that time able to create servers which could use Atom or Xeon chips in the same infrastructure.  AMD developed compatibility with their existing Opteron chips and it was thought that this would be a perfect platform to launch Seattle, their hybrid 64bit ARM chips on.  Unfortunately with the poor revenue that AMD has seen means that the SeaMicro server division is being cut so they can focus on their other products.  Lisa Su obviously has more information that we do on the performance of AMD but it seems counter-intuitive to shut down the only business segment to make positive income, but as The Register points out the $45m which they made is down almost 50% from this time last year.  AMD will keep the fabric patents but as of now we do not know if they are looking to sell their server business, license the patents or follow some other business plan.

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"Tattered AMD says it's done with its SeaMicro server division, following a grim quarter that saw the ailing chipmaker weather losses beyond the expectations of even the gloomiest of Wall Street analysts."

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Source: The Register

Hints of things to come from AMD

Subject: General Tech | March 31, 2015 - 12:18 PM |
Tagged: skybridge, HPC, arm, amd

The details are a little sparse but we now have hints of what AMD's plans are for next year and 2017. In 2016 we should see AMD chips with ARM cores, the Skybridge architecture which Josh described almost a year ago, which will be pin compatible allowing the same motherboard to run with either an ARM processor or an AMD64 depending on your requirements.  The GPU portion of their APUs will move forward on a two year cycle so we should not expect any big jumps in the next year but they are talking about an HPC capable part by 2017.  The final point that The Register translated covers that HPC part which is supposed to utilize a new memory architecture which will be nine times faster than existing GDDR5.

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"Consumer and commercial business lead Junji Hayashi told the PC Cluster Consortium workshop in Osaka that the 2016 release CPU cores (an ARMv8 and an AMD64) will get simultaneous multithreading support, to sit alongside the clustered multithreading of the company's Bulldozer processor families."

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Source: The Register

AMD hits the peak of performance in gaming and productivity

Subject: General Tech | August 7, 2014 - 12:45 PM |
Tagged: HPC, amd, firepro, S9150, S9050, opencl

The new cooling on the 290X tends to have it at the top of the gaming charts and with the impending release of two new FirePro HPC cards AMD looks to take the productivity title away from the Tesla K40.  The higher end S9150 boasts 16GB GDDR5 memory with a 512-bit memory interface, 44 GCN compute units with 64 stream processors each there is a total of 2816 stream processors on board.  That equates to 5.07 TFLOPS peak single-precision  2.53 TFLOPS peak double-precision performance with theoretical memory bandwidth of 320GB per second.  AMD expects the S9150 to have support for OpenCL 2.0 drivers by the end of the year, which the lower priced and specced S9050 will not though both will support AMD Stream technology and OpenCL 1.2.  Check them out at The Register.

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"The company's new big gun is the FirePro S9150 card, which maxes out at a blistering 5.07 TFLOPS peak single-precision floating-point performance and 2.53 TFLOPS peak double-precision performance."

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Source: The Register

How about a little High Powered Computing?

Subject: General Tech | July 2, 2014 - 02:58 PM |
Tagged: HPC, ISS

The Register visited this years ISS and snapped some pictures of the hardware that was on display.  There were a lot of storage solutions being demonstrated like the Silent Brick Library from Fast LTA which offers an alternative to tape archives with the ability to can hold up to 60TB of uncompressed data with 12 bricks in a rack mounted device.  Samsung had a brief presentation on 3D V-NAND but did not reveal anything new about their new type of NAND.  AMD showed off their new W9100 FirePro and quite a few vendors, Intel included, are increasing their usage of watercooling in racks.  Click over to see the latest expensive HPC gear.

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"The International Supercomputer Show in Leipzig, Germany, was full of fascinating things at the high-end grunt front of the computing business. Here's what attracted this roving hack's eye."

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Source: The Register

Fibre at 32 gigabits per second comes a little closer

Subject: General Tech | December 9, 2013 - 12:47 PM |
Tagged: interconnect, fibre optics, 32 Gbps, HPC

With new emphasis on building modular HPC machines from multitudes of low powered processors working in parallel interconnect technology needs to provide immense amounts of bandwidth.   This is becoming much closer to reality as 32 Gbps channel is undergoing standardization and will likely be quickly accepted and certified.  Products using this standard are still a year or more from market but will likely be quickly adopted by companies who depend on large arrays of VMs.  According to the roadmap on The Register 64 Gbps is already starting development with 2016 as a possible goal for its standardization process to begin.

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"The Association has let it be known that the “INCITS T11 standards committee has recently completed the Fibre Channel Physical Interface - sixth generation (FC-PI-6) industry standard for specifying 32 Gigabit per second (Gbps) Fibre Channel and will forward it to the American National Standards Institute (ANSI) for publication in the first quarter of 2014."

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Source: The Register

Please Tip Your Server of Raspberry Pi. 5V DC Customary.

Subject: General Tech, Storage | July 18, 2013 - 04:56 PM |
Tagged: Raspberry Pi, nvidia, HPC, amazon

Adam DeConinck, high performance computing (HPC) systems engineer for NVIDIA, built a personal computer cluster in his spare time. While not exactly high performance, especially when compared to the systems he maintains for Amazon and his employer, its case is made of Lego and seems to be under a third of a cubic foot in volume.

It is a cluster of five Raspberry Pi devices and an eight-port Ethernet switch.

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Image source: NVIDIA Blogs

Raspberry Pi is based on a single-core ARM CPU bundled on an SoC with a 24 GFLOP GPU and 256 or 512 MB of memory. While this misses the cutesy point of the story, I am skeptical of the expected 16W power rating. Five Raspberry Pis, with Ethernet, draw a combined maximum of 17.5W, alone, and even that neglects the draw of the networking switch. My, personal, 8-port unmanaged switch is rated to draw 12W which, when added to 17.5W, is not 16W and thus something is being neglected or averaged. Then again, his device, power is his concern.

Despite constant development and maintenance of interconnected computers, professionally, Adam's will for related hobbies has not been displaced. Even after the initial build, he already plans to graft the Hadoop framework and really reign in the five ARM cores for something useful...

... but, let's be honest, probably not too useful.

Source: NVIDIA Blogs

Inspur Readies Tianhe-2 Supercomputer With 54 Petaflop Theoretical Peak Performance

Subject: Systems | June 3, 2013 - 09:27 PM |
Tagged: Xeon Phi, tianhe-2, supercomputer, Ivy Bridge, HPC, China

A powerful new supercomputer constructed by Chinese company Inspur is currently in testing at the National University of Defense Technology. Called the Tianhe-2, the new supercomputer has 16,000 compute nodes and approximately 54 Petaflops of peak theoretical compute performance.
Destined for the National Supercomputer Center in Guangzhou, China, the open HPC platform will be used for education and research projects. The Tianhe-2 is composed of 125 racks with 128 compute nodes in each rack.

The compute nodes are broken down into two types: CPM and APU modules. One of each node type makes up a single compute board. The CPM module hosts four Intel Ivy Bridge processors, 128GB system memory, and a single Intel Xeon Phi accelerator card with 8GB of its own memory. Each APU module adds five Xeon Phi cards to every compute board. The compute boards (a CPM module + a APU module) contain two NICs that connect the various compute boards with Inspur's custom THExpress2 high bandwidth interconnects. Finally, the Tianhe-2 supercomputer will have access to 12.4 Petabytes of storage that is shared across all of the compute boards.

In all, the Tianhe-2 is powered by 32,000 Intel Ivy Bridge processors, 1.024 Petabytes of system memory (not counting Phi dedicated memory--which would make the total 1.404 PB), and 48,000 Intel Xeon Phi MIC (Many Integrated Cores) cards. That is a total of 3,120,000 processor cores (though keep in mind that number is primarily made up of the relatively simple individual Phi cores as there are 57 cores to each Phi card).

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Inspur claims up to 3.432 TFlops of peak compute performance per compute node (which, for simplicity they break down as one node is 2 Ivy Bridge chips, 64GB memory, and 3 Xeon Phi cards although the two compute modules that make up a node are not physically laid out that way) for a total theoretical potential compute power of 54,912 TFlops (or 54.912 Petaflops) across the entire supercomputer. In the latest Linpack benchmark run, researchers saw up to 63% efficiency in attaining peak performance -- 30.65 PFlops out of 49.19 PFlops peak/theoretical performance -- when only using 14,336 nodes with 50GB RAM each. Further testing and optimization should improve that number, and when all nodes are brought online the real world performance will naturally be higher than the current benchmarks. With that said, the Tianhe-2 is already besting Cray's TITAN, which is promising (though I hope Cray comes back next year and takes the crown again, heh).

In order to keep all of this hardware cool, Inspur is planning a custom liquid cooling system using chilled water. The Tianhe-2 will draw up to 17.6 MW of power under load. Once the liquid cooling system is implemented the supercomputer will draw 24MW while under load.
This is an impressive system, and an interesting take on a supercomputer architecture considering the rise in popularity of heterogeneous architectures that pair massive numbers of CPUs with graphics processing units (GPUs).

The Tianhe-2 supercomputer will be reconstructed at its permanent home at the National Supercomputer Center in Guangzhou, China once the testing phase is finished. It will be one of the top supercomputers in the world once it is fully online! HPC Wire has a nice article with slides an further details on the upcoming processing powerhouse that is worth a read if you are into this sort of HPC stuff.

Also read: Cray unveils the TITAN supercomputer.

Source: HPC Wire

NVIDIA's plans for Tegra and Tesla

Subject: General Tech | April 24, 2013 - 01:38 PM |
Tagged: Steve Scott, nvidia, HPC, tesla, logan, tegra

The Register had a chance to sit down with Steve Scott, once CTO of Cray and now CTO of NVIDIA's Tesla projects to discuss the future of their add-in cards as well as that of x86 in the server room.  They discussed Tegra and why it is not receiving the same amount of attention at NVIDIA as Tegra is, as well as some of the fundamental differences in the chips both currently and going forward.  NVIDIA plans to unite GPU and CPU onto both families of chips, likely with a custom interface as opposed to placing them on the same die, though both will continue to be designed for very different functions.  A lot of the article focuses on Tegra, its memory bandwidth and most importantly its networking capabilities as it seems NVIDIA is focused on the server room and providing hundreds or thousands of interconnected Tegra processors to compete directly with x86 offerings.  Read on for the full interview.

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"Jen-Hsun Huang, co-founder and CEO of Nvidia has been perfectly honest about the fact that the graphics chip maker didn't intend to get into the supercomputing business. Rather, it was founded by a bunch of gamers who wanted better graphics cards to play 3D games. Fast forward two decades, though, and the Nvidia Tesla GPU coprocessor and the CUDA programming environment have taken the supercomputer world by storm."

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Source: The Register

IDF: Intel Announces Upcoming Haswell and Ivy Bridge-E Xeon Processors

Subject: General Tech | April 10, 2013 - 04:14 PM |
Tagged: xeon-ex, xeon-ep, xeon, server, Intel, HPC, haswell

Intel officially announced its next-generation Xeon processors at IDF Beijing today. The new lineup includes the Haswell-based Xeon E3 1200 V3 family on the low end, and the Ivy Bridge-EP Xeon E5 and Ivy Bridge-EX Xeon E7 aimed at the mid-range general purpose and high-end HPC markets respectively. Intel did not disclose pricing or details on the new chips (such as core counts, cache, clockspeeds, number of SKUs etc.). However, the x86 chip giant did state that the new chips are coming later this year as well as teasing a few tidbits of information on the new Xeon chips.

The upcoming Xeon E3 processors will be part of the Xeon E3 1200 V3 family. These chips will be based on Haswell and are limited to one socket per board. Thanks to the Haswell architecture, Intel has managed to reduce power consumption by approximately 25% and increase video transcoding performance by about 25%. There will be at least one Xeon E3 1200 V3 series chip with a 13W TDP, for example.

Intel is also releasing a new media software development kit (SDK) for Linux and Windows machines that will provide a common platform for developers. It has allowed Intel to maximize the use of both the CPU and GPU for HD video transcoding as well as increasing the number of simultaneous video transcodes over previous generations. The new Xeon E3 1200 V3 (Haswell) chips will be available sometime before the end of 2013.

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The next-generation Xeon E5 chips will be based on the 22nm Ivy Bridge-EP architecture. They will be positioned at general purpose computing in data centers (and possibly high-end workstations), and will be limited to 2 sockets per motherboard. The new Xeon E5 processors will incorporate Intel Secure Key and OS Guard technologies. OS Guard is the evolution of the company's existing Intel Execute Disable Bit security technology. Intel is also including AES-NI (AES-New Instructions), to improve the hardware acceleration of AES encrypt/decrypt operations. These mid-range Xeon chips will be available in Q3 2013.

Finally, the top-end Xeon E7 processors will be based on the 22nm Ivy Bridge-EX architecture. The upcoming processors are intended for high performance server and supercomputing applications where scalability and performance are important. The Ivy Bride-EX chips are compatible with motherboards that will have between 4 and 8 sockets and up to 12TB of RAM per node. Further, Intel has packed these processors with new RAS features, including Resilient System Technology and Resilient Memory Technology. The RAS features ensure stability and data integrity in calculations are maintained. Such features are important in scientific, real-time analytics, cloud computing, and banking applications, where performance and up-time are paramount and any errors could cost a company money. Intel has stated that the new Xeon E7 CPUs will be available in the fourth quarter of this year (Q4'13).

While I was hoping for more details as far as core count, clockspeeds, and pricing, the approximate release to market timeframe for the chips is known. Do you think you will be upgrading to the new Xeon chips later this year, or are your current processors fast enough for your server applications?

More information on the upcoming Xeon chips can be found in this Intel fact sheet (PDF).

Source: Intel (PDF)

GTC 2013: TYAN Launches New HPC Servers Powered by Kepler-based Tesla Cards

Subject: General Tech, Graphics Cards | March 19, 2013 - 06:52 PM |
Tagged: GTC 2013, tyan, HPC, servers, tesla, kepler, nvidia

Server platform manufacturer TYAN is showing off several of its latest servers aimed at the high performance computing (HPC) market. The new servers range in size from 2U to 4U chassis and hold up to 8 Kepler-based Tesla accelerator cards. The new product lineup consists of two motherboards and three bare-bones systems. The S7055 and S7056 are the motherboards while the FT77-B7059, TA77-B7061, and FT48-B7055.

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The TA77-B7061 is the smallest system, with support for two Intel Xeon E5-2600 processors and four Kepler-based Tesla accelerator cards. The FT48-B7055 has si7056 specifications but is housed in a 4U chassis. Finally, the FT77-B7059 is a 4U system with support for two Intel Xeon E5-2600 processors, and up to eight Tesla accelerator cards. The S7055 supports a maximum of 4 GPUs while the S7056 can support two Tesla cards, though these are bare boards so you will have to supply your own cards, processors, and RAM (of course).

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According to TYAN, the new Kepler-based HPC systems will be available in Q2 2013, though there is no word on pricing yet.

Stay tuned to PC Perspective for further GTC 2013 Coverage!