Subject: General Tech | November 28, 2013 - 01:48 PM | Jeremy Hellstrom
Tagged: DRAM, HMC, hybrid memory cubes, micron, TSV
Hybrid Memory Cubes are DRAM stacked in layers with logic on the bottom layer to decide which memory layer to address commands to whic is being developed by a team that includes Altera, ARM, IBM, SK Hynix, Micron, Open-Silicon, Samsung and Xilinix. This is intended to give DRAM enhanced parallelization which will help it keep up with today's multi-cored processors. Micron's example which the Register takes a look at here claims up to 10 GB/sec (80 Gb/sec) of bandwidth from each of the 16 vaults present on the chip, a vault being an area of memory on a layer. That compares favourably to the maximum theoretical JEDEC speed of DDR3-1333 which is just a hair over 10GB/s. Read more here.
"Dratted multi-core CPUs. DRAM is running into a bandwidth problem. More powerful CPUs has meant that more cores are trying to access a server’s memory and the bandwidth is running out.
One solution is to stack DRAM in layers above a logic base layer and increase access speed to the resulting hybrid memory cubes (HMC), and Micron has done just that."
Here is some more Tech News from around the web:
- Prolonged Ivy Bridge life-cycle affects Intel 2014 CPU roadmap @ DigiTimes
- Repairing Dead USB Flash Drives @ Hack a Day
- Globalfoundries gearing up for high-volume MEMS manufacturing @ DigiTimes
- Gigabyte expected to post 28-year shipments high of 21 million motherboards in 2013 @ DigiTimes
- THOUSANDS of Ruby on Rails sites leave logins lying around @ The Register
- How to Remote Control Your Camera with Darktable on Linux @ Linux.com
Subject: Memory | October 7, 2011 - 08:52 AM | Tim Verry
Tagged: memory, hybrid memory cube, HMC, micron, Intel, Samsung, ram, DDR, DRAM
Micron Technology and Samsung Electronics, in cooperation with Intel, Altera Corporation, Open Silicon, and Xilinx among others have formed the “Hybrid Memory Cube Consortium” to develop and encourage adoption of a new storage interface specification. This new storage technology is based on Hybrid Memory Cube (HMC) technology, which is comprised of PCB, a thin logic layer, and stacks of DRAM chips. These memory chips are stacked vertically on top of one another and connected via TSV.
A mock up of a HMC (Source: CNET)
According to Tech Connect Magazine, Micron’s Vice President for DRAM Marketing is quoted in stating “HMC brings a new level of capability to memory that provides exponential performance and efficiency gains.” Hybrid Memory Cube technology is claimed to be capable of using 70% less power than current DDR3 memory modules (DIMMs) while being up to 15 times faster.
Reinforcing Micron’s position is Intel’s CTO Justin Rattner who talked very highly of the technology and it’s massive bandwidth and I/O improvements versus traditional DDR style memory designs. The Hybrid Memory Cube is capable of sustained transfer rates of 1 terabit per second, and is “the most energy efficient DRAM ever built” by a bits transferred per amount of energy consumed.
Both Intel and Micron have expressed that the HMC technology will be a boon for data centers and high performance computing that demands low power and high bandwidth memory storage. Assuming the numbers pan out, the Hybrid Memory Cube will be quite a leap in memory efficiency and will further accelerate adoption rates of so called “cloud” applications as well as more efficient high performance servers used in scientific research endeavors. All in all, the idea of the Hybrid Memory Cube is cool stuff, and it will be interesting to see if the actual memory will live up to its grandeur name.